PLDA XpressGX5LP-SE, Справочное руководство

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Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual
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3.4 PCI Express Endpoint Connector
The PCI Express male connector enables access to Endpoint PCI Express components as a x1, x4, or x8 PCI
Express 2.0/3.0 Link.
Figure 7: PCI Express connector
The table below describes pin assignments for the PCI Express Endpoint connector. Shaded signals are defined
as optional by the
PCI Express Card Electromechanical Specification 2.0 , and signals that appear bold are active
signals implemented on the XpressGX5LP-SE.
Side B Side A
PCI Express
Pin
FPGA Pin Signal
PCI Express
Pin
FPGA Pin Signal
1 -- +12V 1 connected to
mPRSNT#2 mPRSNT1#
2 -- +12V 2 -- +12V
3 -- +12V 3 -- +12V
4 -- GND 4 -- GND
5 MAX2 - J8 Sm_clk 5 nc JTAG2
6 MAX2 - H8 Sm_dat 6 nc JTAG3
7 -- GND 7 nc JTAG4
8 -- +3.3V 8 nc JTAG5
9 nc JTAG1 9 -- +3.3V
10 Linked to 3.3V
via a jumper 3.3Vaux 10 -- +3.3V
11 nc mWAKE# 11 AC28 mPERST #
-- -- -- -- -- --
12 -- RSVD 12 -- GND
13 -- GND 13 AF34 PCIe_CLKp
14 AV38 mPERp0 14 AF35 PCIe_CLKn
15 AV39 mPERn0 15 -- GND
Table 7: Pin assignments for the PCI Express endpoint connector