PDP-5000EX
194
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Function
No.
Mark
Pin Name
I/O
Pin Function
Active
46
A10
A9
External address bus
47
A11
A10
External address bus
48
A12
A11
External address bus
49
A13
A12
External address bus
50
A14
A13
External address bus
51
A15
A14
External address bus
52
VCEE
−
Power supply (+3.3 V)
53
VSS
−
GND
54
VCCI
−
Power supply (+1.8 V)
55
A16/P50
A15
External address bus
56
A17/P51
A16
External address bus
57
A18/P52
A17
External address bus
58
A19/P53
A18
External address bus
59
A20/P54
A19
External address bus
60
A21/P55
NC
O
61
A22/P56
ELITE_DET
I
ELITE model (North America)/ADVANCE model (Europe)/China model (General)/HDD (country) distinction
H
62
A23/P57
APPLI_ON
I
Detect connection of the ASIC examination jig
L
63
VCEE
−
Power supply (+3.3 V)
64
X0
I
Clock input
65
VSS
−
GND
66
X1
O
Clock output
67
VCCI
−
Power supply (+1.8 V)
68
INTX
RESET
I
External reset input
69
MD0
MD0
I
Operation mode setting L fixing
70
MD1
MD1
I
Operation mode setting H fixing (not USB)
71
MD2
MD2
I
Operation mode setting L: Normal, H: at writing
72
MD3
MD3
I
Operation mode setting L fixing
73
AVCC
−
Power supply for A/D
74
AVRH
−
Reference power supply for A/D
75
AVSS/AVRL
−
GND for A/D
76
AN0
TEMP2
I
(A/D) Temperature sensor Outside temperature
AD
77
AN1
NC
I
−
AD
78
AN2/PF0
MODE
I
(A/D) Operation mode distinction
AD
79
AN3/PF1
NC
O
−
L
80
AN4/PF2
RST_FPGA
O
Initialization of F.F. in the FPGA (after CONF_DONE)
L
81
AN5/PF3
NC
O
−
L
82
AN5/PF4
RST4
I
For abnormal operation detection Monitor V+12V
L
83
AN7/PF5
DSUB_DET
I
PC V sync. signal detection
H
84
AN8/PF6
A_STBY_B
O
AUDIO power AMP ON/OFF
H
85
AN9/PF7
REQ_MVDEC
I
Modification information of the various detection result as the frequency judgments
L
86
ICS0
ICS0
Status output for development tool
87
ICS1
ICS1
Status output for development tool
88
ICS2
ICS2
Status output for development tool
89
ICD0
ICD0
Data output for development tool
90
ICD1
ICD1
Data output for development tool
91
ICD2
ICD2
Data output for development tool
92
ICD3
ICD3
Data output for development tool
93
IBREAK
IBREAK
Break for development tool
94
ICLK
ICLK
Clock for development tool
95
TRSTX
TRSTX
Reset for development tool
Содержание PDP-5000EX
Страница 38: ...PDP 5000EX 38 1 2 3 4 1 2 3 4 C D F A B E 4 BLOCK DIAGRAM AND SCHEMATIC DIAGRAM 4 1 OVERALL WIRING DIAGRAM ...
Страница 41: ...PDP 5000EX 41 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 42: ...PDP 5000EX 42 1 2 3 4 1 2 3 4 C D F A B E 4 2 2 MULTI BASE SECTION BLOCK DIAGRAM MULTI BASE SECTION ...
Страница 43: ...PDP 5000EX 43 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 44: ...PDP 5000EX 44 1 2 3 4 1 2 3 4 C D F A B E 4 3 FHD MAIN ASSY FHD MAIN ASSY ...
Страница 45: ...PDP 5000EX 45 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 46: ...PDP 5000EX 46 1 2 3 4 1 2 3 4 C D F A B E 4 4 50FHD X DRIVE ASSY 50FHD X DRIVE ASSY ...
Страница 47: ...PDP 5000EX 47 5 6 7 8 5 6 7 8 C D F A B E from Power supply X Drive power supply map ...
Страница 48: ...PDP 5000EX 48 1 2 3 4 1 2 3 4 C D F A B E 4 5 50FHD Y DRIVE ASSY 50FHD Y DRIVE ASSY ...
Страница 51: ...PDP 5000EX 51 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 54: ...PDP 5000EX 54 1 2 3 4 1 2 3 4 C D F A B E 4 9 POWER SUPPLY UNIT POWER SUPPLY UNIT ...
Страница 167: ...PDP 5000EX 167 5 6 7 8 5 6 7 8 C D F A B E 10 3 LED INFORMATION LED Pattern State LED Pattern ...