DVH-335UB/XNRC
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8.2 PCL OUTPUT CONFIRMATION
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PCL output
In the normal operation mode (with the detachable panel installed, the ACC switched ON, the standby mode
cancelled), shift the TESTIN IC601(Pin 86) terminal to H.
The clock signal is output from the PCL terminal IC601(Pin 37).
The frequency of the clock signal is 468 750 Hz that is one 32th of the fundamental frequency.
The clock signal should be 468 750 Hz (- 10 Hz, + 15 Hz)
If the clock signal out of the range, the X’tal (X601) should be replaced with new one.
Содержание DVH-335UB/XNRC
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Страница 45: ...DVH 335UB XNRC 45 5 6 7 8 5 6 7 8 C D F A B E Side A COMPOSITE GNDV Fig 11 3 VIDEO signal check point ...
Страница 48: ...DVH 335UB XNRC 48 1 2 3 4 1 2 3 4 C D F A B E Side A DGND1 IC1501 50pin Fig 13 3 48 MHz check point ...
Страница 50: ...DVH 335UB XNRC 50 1 2 3 4 1 2 3 4 C D F A B E Side A SCLOCK SDATA D CP_ RESET D DGND2 ...
Страница 56: ...DVH 335UB XNRC 56 1 2 3 4 1 2 3 4 C D F A B E 5 5 CONNECTOR FUNCTION DESCRIPTION ...
Страница 66: ...DVH 335UB XNRC 66 1 2 3 4 1 2 3 4 C D F A B E 1 Have a specified part Handling OK Handling NG How to have it ...
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Страница 84: ...DVH 335UB XNRC 84 1 2 3 4 1 2 3 4 C D F A B E 9 3 EXTERIOR 2 A 601 A B B A ID ...
Страница 88: ...DVH 335UB XNRC 88 1 2 3 4 1 2 3 4 C D F A B E A GEM1045 B GEM1038 C GEM1024 A C C A A C C C C C A A ...
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