Phytec phyCORE-PXA270, Руководство по оборудованию

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Carrier Board phyCORE-PXA270
26
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
Control registers 6 and 7 contain the interrupt sources for the
controller's interrupt input GPIO_9. In control register 6 the register
bits are cleared when one of the external interrupt sources becomes
active. If one of the 4 bits in this register is 0, then a high-active
interrupt is generated on GPIO_9. The value 0xFF has to be written to
this control register after the interrupt has been serviced in order to
allow new interrupts to occur. The interrupt control register 7 is used
to mask individual interrupt inputs. Only if the corresponding bit is set
to 1, an external interrupt will clear the bit in control register 6. The
interrupt sources correspond to the bit name in control register 7.
REG ADDR D7-D4 D3 D2 D1 D0
CTRL 6 0x0400000C Res INT3 INT2 INT1 INT0
RW R/W=0 R/W R/W R/W R/W
CTRL 7 0x0400000E Res INT
PM_5V INT
MMCDET INT
FF_RI INT
BT_DET
RW R/W=0 R/W R/W R/W R/W
Signal
Name 5V_OFF MMC_DET
2
FF_RI_DE
TECT BT_RXD_D
ETECT
Table 14: PLD U7 Control Registers 6 and 7
INT0 IRQ status bit for BT-UART detect
INT1 IRQ status bit for FF-UART detect
INT2 IRQ status bit for MMC-Card 2 detect
INT3 IRQ status bit for 5 V power not present
Clear bit = interrrupt active if one of the four bits = 0 => /INT0-BIT
INT_BT_DET Enable bit for BT-UART detect
INT_FF_DET Enable bit for FF-UART detect
INT_MMCDET Enable bit for MMC card 2 detect
INT_PM5V Enable bit for 5 V power not present
Only if the corresponding bit is set to "1", then an interrupt will clear
the matching bit in control register 6 and hence release an interrupt.