Phytec phyCORE-OMAP44 Series, Руководство по оборудованию

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phyCORE-OMAP44xx Part II: PCM-959/phyCORE-OMAP44xx Carrier Board
L-760e_1 © PHYTEC Messtechnik GmbH 2012 149
2.1.3.21.6 SPI2 Signal Mapping
The second SPI interface is derived from the Multichannel Audio Serial (McASP) interface pins of the
phyCORE-OMAP44xx as these pins embody the signals of the second SPI module SPI2 as alternative function.
However, if the pins of the expansion connector listed in the following table are intended to be used as
Multichannel Audio Serial interface, it must be noted that all signals required for the second SPI interface are
translated from 1.8 V to 3.3V. Only signal X_McASP_AMUTEIN_GPIO_117 (mute in from external) is at the
original voltage level of 1.8 V.
Compared with the first SPI interface on the carrier board the second SPI interface provides only one chip select
signal (CS0).
2.1.3.21.7 UART1 Signal Mapping
The expansion connector X5 provides the UART1 Interface of the phyCORE-OMAP44xx.
Signal Extension
Bus I/O SL Description
X_McASP_AMUTEIN_GPIO_117 X5D15 I 1.8 V Mute in from external at 1.8 V
McSPI2_CLK_3V3 X5D16 I/O 3.3 V SPI2 Interface Clock / McASP
transmit high frequency master
clock (McASP_AHCLKX)
McSPI2_SOMI_3V3 X5D17 I/O 3.3 V SPI2 Interface SOMI / McASP
audio transmit data (McASP_AXR)
McSPI2_SIMO_3V3 X5D18 I/O 3.3 V SPI2 Interface SIMO / McASP
mute out to external
(McASP_AMUTE)
McSPI2_CS0_3V3 X5D19 I/O 3.3 V SPI2 Interface Chip Select 0 /
McASP transmit frame synchroni-
zation (McASP_AFSX)
/SPI2_RDY_3V3 X5D20 I/O 3.3 V SPI2 Interface Ready / McASP
transmit bit clock (McASP_ACLKX)
Table 75: SPI2 (McASP) Signal Mapping
Signal Extension Bus I/O SL Description
X_UART1_TX X5C35 O 1.8 V UART1 transmit
X_UART1_RX X5C36 I 1.8 V UART1 receive
Table 76: UART1 Signal Mapping