Phytec phyCORE-i.MX31, Руководство по оборудованию

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phyCOREi.MX31
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PHYTEC Messtechnik GmbH 2007 L-700e_0
7.2 LP-DDR-SDRAM (U5-U8)
The phyCORE-i.MX31 can use one, or both of the LP-DDR-SDRAM banks on the i.MX31 depending
on the SDRAM population density options.
Each RAM bank is comprised of two 16-bit wide DDR-SDRAM chips, configured for 32-bit access,
and operating at 133MHz. In lower density configurations, U5 and U7 populate the module and are
accessed via SDRAM memory bank 0 using chip select signal /CSD0 starting at 0x8000 0000. In
higher density configurations, U6 and U8 are also populated and are accessed via SDRAM memory
bank 1 using chip select signal /CSD1 starting at 0x9000 0000.
If RAM bank U6/U8 is unpopulated then the /CSD1 chip select line is freed and can be used as /CS3.
Typically the LP-DDR-SDRAM initialization is performed by a boot loader or operating system
following a power-on reset and must not be changed at a later point by any application code. When
writing custom code independent of an operating system or boot loader, SDRAM must be initialized
by accessing the appropriate SDRAM configuration registers on the i.MX31 controller. Refer to the
i.MX31 User Manual for accessing and configuring these registers.