Phytec 1488.2, Руководство по оборудованию

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PCM-065/phyCORE-i.MX8X System on Module L-864e.A1
© PHYTEC America LLC, 2021 47
6.7 SPDIF
The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive
and transmit digital audio. The SPDIF transceiver allows the handling of both SPDIF channel status (CS) and
User (U) data and includes a frequency measurement block that allows the precise measurement of an incoming
sampling frequency.
Table 31. SPDIF Connections at the phyCORE-Connector
X1
Pin # Processor
Signal
SOM Signal Type Level
Processor
Ball
Description
B51 SPDIF0_RX X_SPDIF0_RX/ENET1_RGMII_RXD0 I 1.8V F24 SPDIF Receive
B52 SPDIF0_TX X_SPDIF0_TX/ENET1_RGMII_RX_CTL O 1.8V J23 SPDIF Transmit
B53 SPDIF0_EXT_CLK
X_SPDIF0_EXT_CLK/ENET1_REFCLK_
125M_25M
I 1.8V E27
SPDIF External
Clock
6.8 SPI
The Serial Peripheral Interface (SPI) is a transmit/receive, master/slave synchronous serial bus. The phyCORE-
i.MX8X SOM provides access to four SPI ports at the phyCORE-Connector.
Table 32. SPI Connections at the phyCORE-Connector
X1 Pin # Processor Signal SOM Signal Type Level Processor Ball Description
A27 SPI0_SCK X_SPI0_SCK I/O 3.3V P30 SPI0 Clock
A26 SPI0_CS0 X_SPI0_CS0 I/O 3.3V R33 SPI0 Chip Select 0
A28 SPI0_CS1 X_SPI0_CS1 I/O 3.3V R35 SPI0 Chip Select 1
A29 SPI0_SDO X_SPI0_SDO O 3.3V R31 SPI0 Data Out
A30 SPI0_SDI X_SPI0_SDI I 3.3V P34 SPI0 Data In
A35 SPI1_SCK X_SAI0_TXC I/O 3.3V J35 SPI1 Clock
A34 SPI1_CS0 X_SAI0_TXFS I/O 3.3V L33 SPI1 Chip Select 0
A37 SPI1_CS1 X_SAI1_RXD I/O 3.3V M32 SPI1 Chip Select 1
A32 SPI1_SDO X_SAI0_RXD O 3.3V M34 SPI1 Data Out
A33 SPI1_SDI X_SAI0_TXD I 3.3V K34 SPI1 Data In
A22 SPI2_SCK X_SPI2_SCK I/O 3.3V R29 SPI2 Clock
A21 SPI2_CS0 X_SPI2_CS0 I/O 3.3V P28 SPI2 Chip Select 0
A34 SPI2_CS1 X_SAI0_TXFS I/O 3.3V L33 SPI2 Chip Select 1
A23 SPI2_SDI X_SPI2_SDI I 3.3V N31 SPI2 Data In
A24 SPI2_SDO X_SPI2_SDO O 3.3V P32 SPI2 Data Out
B57 SPI3_SCK X_SPI3_SCK I/O 3.3V D28 SPI3 Clock
B55 SPI3_CS0 X_SPI3_CS0 I/O 3.3V D26 SPI3 Chip Select 0
B56 SPI3_CS1 X_SPI3_CS1 I/O 3.3V F28 SPI3 Chip Select 1
B58 SPI3_SDI X_SPI3_SDI I 3.3V H24 SPI3 Data In
B59 SPI3_SDO X_SPI3_SDO O 3.3V G25 SPI3 Data Out
6.9 UART
The Universal Asynchronous Receiver/Transmitter module is a slave peripheral that utilizes DMA for data
transfer or interrupt polling via a host CPU. There are six UART modules provided and each can be used for
configuration and data exchange with external peripheral devices.
SCU UART is dedicated to the SCU and not available for general use.