Circuit Diagrams and PWB Layouts
10.
Main Board: Panel Interface Sequoia
5
4
3
2
1
D
C
B
A
A
LVD
LVD
LVD
LVD
LVDS_E_CLK-
LVD
LVDS_E_CH2-
LVDS_E_CH0-
LVDS_E_CH3-
LVDS_E_CH1-
LVDS_E_CH4-
LVD
LVDS_O_CH4-
LVD
LVDS_O_CH3-
LVD
LVDS_O_CH2-
LVD
LVD
LVDS_O_CLK-
LVD
LVD
LVDS_O_CH1-
LVDS_O_CH0-
PBIAS
PPWR
LVD
LVD
LVD
LVD
LVDS_E_CLK-
LVD
LVDS_E_CH2-
LVDS_E_CH0-
LVDS_E_CH3-
LVDS_E_CH1-
LVDS_E_CH4-
LVD
LVDS_O_CH4-
LVD
LVDS_O_CH3-
LVD
LVDS_O_CH2-
LVD
LVD
LVDS_O_CLK-
LVD
LVD
LVDS_O_CH1-
LVDS_O_CH0-
PBIAS
PPWR
LVD 12
LVDS_O_CH0- 12
LVD 12
LVDS_O_CH1- 12
LVD 12
LVDS_O_CH2- 12
LVD 12
LVDS_O_CH3- 12
LVD 12
LVDS_O_CH4- 12
LVD 12
LVDS_O_CLK- 12
LVDS_E_CH0- 12
LVD 12
LVDS_E_CH1- 12
LVD 12
LVD 12
LVDS_E_CH2- 12
LVD 12
LVDS_E_CH3- 12
LVD 12
LVDS_E_CH4- 12
LVD 12
LVDS_E_CLK- 12
PPWR
12
+3.3V_LVDS 12,19
PBIAS
20
+3.3V_LVDS
+3.3V_LVDS
Title
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e
b
m
u
N
t
n
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m
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c
o
D
e
z
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o f
WLZSA1 ST FLI32626
D2A
Panel Interf_SEQUOIA
PROJECT NAME:
WLZR-A1
A4
11
22
Thursday, January 08, 2009
+
C184
22uF/6.3V
1
2
SEQUOIA LVDS /
TTL
U8E
FLI32626H
LVDS_O_CH0N
Y18
LVDS_O_CH0P
AA18
LVDS_O_CH1P
AC18
LVDS_O_CH1N
AB18
LVDS_O_CH2P
AA17
LVDS_O_CH2N
Y17
LVDS_O_CH3P
AC17
LVDS_O_CH3N
AB17
LVDS_O_CH4P
AC16
LVDS_O_CH4N
AB16
LVDS_O_CLKP
AA16
LVDS_O_CLKN
Y16
LVDS_E_CH0P
Y15
LVDS_E_CH0N
W15
LVDS_E_CH1P
AB15
LVDS_E_CH1N
AA15
LVDS_E_CH2P
AC14
LVDS_E_CH2N
AC15
LVDS_E_CH3P
AB14
LVDS_E_CH3N
AA14
LVDS_E_CH4P
AC13
LVDS_E_CH4N
AB13
LVDS_E_CLKP
Y14
LVDS_E_CLKN
W14
LVDS_33
W17
LVDS_33
AA13
LVDS_GND
W16
LVDS_GND
W18
PPWR
Y12
PBIAS
W12
C185
1nF/6
C186
0.1uF/6
1
8
4
3
0_509_090202.ep
s
090202