3 - 1
N ame
N o.
I /O
Other
F unction
F unction
Des cription
V
SS
V
DD
11
8
Power supply pin
Supply 2.0 V to 5.5 V to V
DD
and 0 V to V
SS
.
OSC1
OSC2
10
9
Input
Output
Clock input pin
Clock output pin
Connect these oscillation pins to ceramic or crystal
oscillators for high-frequency clock operation.
If the clock is an external input, connect it to OSC1 and
leave OSC2 open. The chip will not operate with an
external clock when using either the STOP or SLOW
modes.
XI
XO
12
13
Input
Output
Clock input pin
Clock output pin
Connect these oscillation pins to crystal oscillators for
low-frequency clock operation.
If the clock is an external input, connect it to XI and leave
XO open. The chip will not operate with an external clock
when using the STOP mode. If these pins are not used,
connect XI to V
SS
and leave XO open.
NRST
32
Input
P27
Reset pin
[Active low]
This pin resets the chip when power is turned on, is
allocated as P27 and contains an internal pull-up
resistor (Typ.35 kW). Setting this pin low initializes the
internal state of the device. Thereafter, setting the input
to high releases the reset. The hardware waits for the
system clock to stabilize, then processes the reset
interrupt. Also, if "0" is written to P27 and the reset is
initiated by software, a low level will be output. The
output has an N-ch open-drain configuration. If a
capacitor is to be inserted between NRST and V
SS
, it
is recommended that a discharge diode be placed
between NRST and V
DD
.
P00
P01
P02
P03
P04
P05
P06
25
26
27
28
29
30
31
I/O
SBO0, TXD
SBI0, RXD
SBT0
SBO1
SBI1
SBT1
NDK, BUZZER
I/O port 0
7-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P0DIR register. A pull-up resistor for each
bit can be selected individually by the P0PLU register.
At reset, the input mode is selected and pull-up resistors
are disabled (high impedance output).
P10
P11
P12
P13
P14
33
34
35
36
37
I/O
RMOUT
TM2IO
TM3IO
TM4IO
I/O port 1
5-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P1DIR register. A pull-up resistor for each
bit can be selected individually by the P1PLU register.
At reset, the input mode is selected and pull-up resistors
are disabled (high impedance output).
PIN DESCRIPTIONS OF IC
MCU MN101C39C_399