Philips LX3950W/01, Руководство по обслуживанию

Страница: 73 / 79

11-23 11-23
Note that the other 2 switches of 7111 (respectively 7111A and
7111B) are unused.
Power supply and power down
The board is having a low drop voltage regulator 7117, which
has an output voltage of 8.3Vdc. The 5 V supply is extracted
via transistor 7119.
Receiver
The blockdiagram of the receiver is as follows:
The power down detection is done via 6105 and 7118. When
the voltage drops the transistor 7118 comes out of saturation
rapidly thereby putting the stereocoder in Hi-Z position (idle)
and no AF output will be there from the stereocoder.
Suitable timing signals for the subcarrier and pilot frequency
are extracted out of a 12 MHz crystal by division with 256 and
512 respectively. The whole chip 7110 can be enabled /
disabled from the synthesiser port P2 (Vpil). (Low = enable).
The outputs are square wave 5 V compatible.
The multiplex output from the stereocoder is fed into a limiter
amplifier 7116B that sets a limit to the output voltage. In case
the audio input signals increase towards 1 .3 V the signal will
be flat-topped and limited symmetrically. This of course
introduces distortion but is necessary in order to observe the
bandwidth limitations as set by legal standards. The base-
emitter junctions of 7120 & 7121 form the limits.
This output signal is then summed with the pilot signal, which is
injected just as a plain square wave. The amplifier 7116A forms
a second order low pass filter that cuts at about 90 kHz. This
reduces the harmonics present in the composite output signal.
This signal is actually fed via trimpotmeter 3179 towards the
varicap in order to achieve FM modulation. Trimpotentiometer
3179 is aligned for a deviation of 50 kHz. There are 3 ways to
align the trimpotmeter:
•
Use a FM modulation analyser meter such as FAM (R&S)
or similar.
•
Put the RF output on a spectrum analyser and connect
both audio inputs together at 0.41 V / 400Hz at the inputs
of the TX. There are 2 peaks visible on the screen. Align
until the difference between the peaks -3 dB is 2* 50kHz
or 100 kHz.
•
Use an accompanying receiver and while modulating both
inputs of the TX align until the measured audio output of
the RX is 1.3 Vrms.
Synthesiser and local oscillator
The internal circuitry of the TSA5060A can be seen in below
figure.
The TSA5060A is software controlled via the I2C bus by the
PIC12C508 microcontroller.
There is no hardware version recognition foreseen but the
version can be read out from the PIC12C508 microcontroller.
There is a different software code for 864, 433 and 914 MHz
version.
The reference quartz is 4 MHz and is divided down to a lower
ref.freq. of 200 KHz or 100KHz (depending on the version). The
PLL filter is passive and includes 2625 – 2626 – 3615-3611-
2612. The transistor 7604 is part of the PLL current source and
allows connection to higher supply voltages as +5V.
The oscillator (LO) is a common base transistor (7603) that is
oscillating at the fundamental frequency. The frequency is
tuned by the varicap 6601 until the tuning voltage is in the
range of the loop filter (between 0.5 and 7 Vdc).
If the voltage is outside this range then possibly the division
ratio is chosen outside the normal range or some freq.
dependant component around the transistor is faulty.
Antenna input
The antenna input is tuned for a 17 cm telescopic antenna. The
input is ESD protected by diode 6602. The SAW filter 1602
protects the receiver for out of band interference.
Figure 1-17 Block diagram receiver
Figure 1-16 Stereocoder
Figure 1-20 Antenna circuit
Figure 1-18 Synthesizer circuit
Figure 1-19 Block diagram TSA5060A
Downconverter
Right out
10V supply
synthesiser TSA5060
PIC12C508A
supply
powersave
I2C data
I2C clock
LA1836M
IF receiver
Stereo decoder
SA572D
expander
NJM4565M
Amplifier
Mute
Left out
4 position channel switch
pin 6
pin 7
pin 4
pin 5
Tuned
pin 2
MUTE
Powersave
pin 3
Stereo
Powersafe supply
CL36532008_078.eps
220403
5n0
5607
2p7
2616
F749
15K 3608
7603
BFR92A
5608
2K2
3618
4K7
3616
7606
BC847B
F749
2p7
2619
5K6 3606
6601
BB151
4p7
2613
3607
220n
2626
2642 220n
5601
1p8
2622
BC847B
7604
13
RFA
14
RFB
6
SCL
5
SDA
12
VCC
2
XTAL
3
XT|COMP
220n 2612
TSA5060ATS
7605
11
ADC
4
AS
1
CP
16
DRIVE
15
GND
10
P0
9
P1
8
P2
7
P3
6K8
3609
16V
10u
2650
100R
3630
5616
3n9
AT-51
1609
4M
220R
3611
2p7
2620
560R
3615
1p0
2623
33p
2655
2615
33p
5617
2u2
2625
18p
2624
1n0
2606
2661 220n 3632
1K0
3631
390R
33p
2618
220R
3610
220n 2627
+8V
CL
DA
+8V
+8V
SYNTHESIZER
OSCILLATOR
CL36532008_079.eps
290403
GND1
I
OGND IGND
O
GND
F704
F704
F703
4 8
2
1
3 6
5
7
864M
B3589 1602
5613
3n3
39p
2630
F703
F748
1n0
5603
33p
2652
6602
BAV99
RT-01T
1750
1
2653
22p
F748
1
2
Hole 3.5 mm
0001
ANTENNA
CL36532008_080.eps
290403
&
3
9
11
13
CT
CT=0
1
Z1
+
STEREO
C O D ER
3
2
1
8
4
10K 3189
7116-A
NJM4565M
3187
22K
NJM4565M
7113-A
3
2
1
8
4
F147
3164
3K3
3191 220R
3190 220R
2196
3n9
BC847B
7121
2174
47p
2170 470p
15K 3175
220p 2177
100n 2182
18K
3151
22n
2165
18K
3152
16V
10u
2171
2195
1n2
8K2
3178
2194
1n5
18K
3150
6K8
3172
2134
33p
F124
4M
1106
AT-51
4u7
2168
2167 220u
82p 2173
3K9
3177
1K0
3183
F125
F131
16V
10u
2153
F144
F145
22p
2151
F150
5
6
7
8
4
3188
4K7
7113-B
NJM4565M
2K2
3131
F146
100n
2135
3169 10K
3165
3K3
680R
3161
2137
100n
100p 2202
4106
BLM21
5133
BC847B
7118
680R
3160
2154
10u
16V
22p
2152
5126
BLM21
100n
2136
27K
3173
22n
2166
2175
1u
F126
3171
680K
2178
22n
BLM21
5125
4105
7
Vss
8
Y0 5
Y1 3 Z 4
11
10
16
VDD
74HC4053D
7111-C
E
6
S 9
Vdd
16
Vee
9
8
GND
12 1
2
3
7
5
4
6
14
13
15
74HC4060
7110
18K
3153
F130
3166 39K
2183 100n
2169
33p
F148
Y1 1 Z 15
Y1 14 Z
74HC4053D
7111-B
E
6
S 10
Vdd
16
Vee
7 Vss
8
Y0 2
7111-A
74HC4053D
6
E
11 S
16
Vdd
7
Vee
8
Vss
12 Y0
13
7116-B
5
6
7
8
4
NJM4565M
F149
33p
2133
10K
3132
3179 10k
680p 2172
15K
470p
2176
3176
82K
3149
270K
3130
7119
BC847B
5130
220u
390R 3182
7120
BC857B
8K2
3174
+8V +8b
pilot
+5V
subc
Vpil
mon_ster
subc
MPX
+8V
+8V
+8V
+8V
+8V
+8V
pilot
+5V
+5V
+5V
+5V
CL 36532008_077.eps
290403
M O D ULA TIO N
LEVEL
FCE717
PRE
AMP
AMP
LOCK
DETECT
DIGITAL PHASE
COMPARATOR
CHARGE PUMP
REFERENCE
DIVIDER
DIVIDER
1/2
17-BIT
DIVIDER
17-BIT LATCH
DIVIDE RATIO
I
2
C-BUS
TRANSCEIVER
1-BIT
LATCH
2-BIT
LATCH
3-BIT
ADC
POWER-ON
RESET
MODE
CONTROL
LOGIC
3-BIT
INPUT
PORTS
4-BIT LATCH
AND
OUTPUT PORTS
XTAL
OSCILLATOR
4-BIT LATCH
2
XTAL
13
RFA
14
RFB
4
AS
6
SCL
5
SDA
11
10 9 8 7
ADC
CP
1
XT/COMP
3
DRIVE
16
VCC
12
GND
15
TSA5060A
P3 P2 P1 P0 CL36532008_071.eps
010503