Philips FTL13U Скачать руководство пользователя

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Circuit Descriptions, Abbreviation List, and IC Data Sheets

EN 152

FTL13U AA & AB

•

Standard single ended signal (TTL).
–

This requires 28 signal lines and more than 14
grounds.

–

Single ended signals up to 3 V.

–

Wide flat ribbon cable.

–

EMI/EMC problems.

–

Feasible up to VGA/NTSC resolution (limited to 250
Mb/s).

•

LVDS
–

Five low voltage (350 mV) differential pairs: one clock
pair and four data pairs.

–

Five grounds.

–

EMI/EMC friendly.

–

WXGA and HD-1280x720p (up to 1 Gb/s).

Figure 9-17 LVDS technology

9.11 Software Upgrading

9.11.1 Introduction

In this chassis, you can

upgrade

the software via ComPair.

This offers the possibility, to replace the entire SW image
without having to remove the flash-memory from the PWB. You
can find more information on how this procedure works in the
ComPair file. It is possible that not all sets are equipped with
the hardware, needed to make software upgrading possible. To
speed up the programming process, the firmware of the
ComPair interface can be upgraded. See Chapter "Service
Modes ...", paragraph "ComPair" - "How To Order" for the order
number.

9.11.2 Specifications

Some specifications are:
•

The upgrade feature makes use of I2C to transfer a new
SW image (4 MB).

•

It requires the ComPair interface Box (RS232 to I2C).

•

The I2C bus is available at the rear side of the set.

•

It uses a ZIP-compressed BIN image to speed up the
transfer process (1/2 size).

•

The complete procedure takes less than 20 minutes with
an upgraded ComPair interface:
–

About 90 seconds to erase a 4 MB flash-memory.

–

Less than 10 minutes to transfer the file (max 1.9 MB).

–

About 5 minutes to decompress/program the flash-
memory.

Note:

It takes about 85 minutes with a standard (not upgraded)

interface.

Constraints:
•

Needs the EPG flash memory, so this device must be
placed also for non-EPG regions like AP and USA.

Advantages:
•

Flexibility.

•

No change in internal ROM (IROM) required (IROM not
used).

•

Flexibility to change of code flash manufacturer as the
"flash driver" is part of the bootstrap code (part of the main
software image).

9.11.3 Concept

Figure 9-18 Memory diagram (initial situation)

The architecture of the OTC microprocessor does not allow the
execution of code from the external RAM. It is also impossible
to write data in the code memory space (there is no instruction
to write data to those memory locations).
The OTC normally boots from its internal ROM (IROM) but
modification of the

internal

ROM software would be too

expensive. Fortunately, the chip architecture allows also the
booting from

external

ROM (XROM).

The IROM is mapped on the first 32 kB of the ROM address
space. The XROM is mapped starting at the same address.
Therefore, the lower 32 kB of XROM overlaps the IROM
memory space.
Via an external pin (EA), it is possible to reveal the XROM
memory below the IROM and so boot using this hidden
software. This is the first trick used by the software upgrade
procedure.

To be able to write to the CODE flash, it is required to address
the device via the RAM address space. Today all RAM but also
the EPG flash is mapped on the RAM address space.
Devices are mapped to the right address space via a few
control lines (kind of chip select). By exchanging the control
lines between the EPG and the CODE flash, it is possible to
map the CODE flash in the RAM address space and at the
same time use the EPG flash to execute software. This is the
second trick used by the procedure.

The main idea is to use the EPG flash to boot up the software
upgrade procedure.
Therefore, the complete procedure relies on the presence of
that one.