Philips DVDR890, Руководство по обслуживанию, Страница: 35 / 116

Diagnostic Software
EN 74 DVDR880-890 /0X1 5.
Error Codes Nucleus 805
5.5 Loop tests
The following loops can be distinguished:
•
Loops performed on the digital board only
• User Dealer loops performed on the digital and analogue
board
• System loops performed via an external connection:
outputs are looped back to the inputs.
Error Code Description Bus Components
0x00 No Error - -
0x11 No link register access PA[8:0] | PAD[7:0] Link | uP
0x12 No link register access or link reset failed PA[8:0] | PAD[7:0] | 1394_RSTn Link | uP | FPGA
0x13 No link register access or link reset failed PA[8:0] | PAD[7:0] | 1394_RSTn Link | uP | FPGA
0x14 No link register access PA[8:0] | PAD[7:0] Link | uP
0x15 No link register access PA[8:0] | PAD[7:0] Link | uP
0x16 No link register access PA[8:0] | PAD[7:0] Link | uP
0x17 Link reset failed 1394_RSTn Link | FPGA
0x18 Link reset failed 1394_RSTn Link | FPGA
0x19 Cycle timer in link chip does not increment - Link
0x1A Interrupt from Link chip does not go low at 8051 LINK_INTn | PINT1n Link | FPGA | uP
0x1B Interrupt from Link chip does not go high at 8051 LINK_INTn | PINT1n Link | FPGA | uP
0x1C Submission of read request to Phy timed out Bus_LP Phy
0x1D Reception of read data from Phy timed out Bus_LP Phy
0x1E Inproper Phy read address was received from Phy Bus_LP Phy
0x1F Phy write timed out Bus_LP Phy
0x20 Could not read reg #2 of Phy Bus_LP Phy
0x21 Could not write 0xaa to reg #1 of phy Bus_LP Phy
0x22 Could not write 0x55 to reg #1 of phy Bus_LP Phy
0x23 Read incorrect default gapcount from Phy Bus_LP Phy
0x24 Read incorrect updated gapcount from Phy Bus_LP Phy
0x25 Read incorrect gapcount from Phy after reset F117 | F173 Phy | OptoPR
0x26 Expecting no 1394 connectivity; while Phy.CNA
indicates connection F108 | PHY_CNA | Bus_PC Phy | OptoCNA | FPGA
0x27 Expecting 1394 connectivity; while Phy.CNA
indicates no connection F108 | PHY_CNA | Bus_PC Phy | OptoCNA | FPGA
0x28 Expected port1 unconnected; but found connected Bus_PC Phy
0x29 Phy read retry limit exceeded - Phy
0x2A Expected port2 unconnected; but found connected - Phy
0x2B Expected port3 unconnected; but found connected - Phy
0x2C Expected 0x1 in lower nibble of Phy reg 7 - Phy
0x2D Expected CPS and C bit set in Phy reg 6 - Phy
0x30 Internal ram problem in address lines Internal in uP P89C51RD2
0x31 Internal ram problem in data lines Internal in uP P89C51RD2
0x32 External ram problem in address lines PA[15:0] | PAD[7:0] | PRDn | PWRn P89C51RD2/CY62256/
74HC573
0x33 External ram problem in data lines PAD[7:0] P89C51RD2/CY62256/
74HC573
0x34 Problem accessing flex scratch register PAD[7:0] EPF6024
0x36 INT0n stuck at '0' PINT0n EPF6024 / P89C51RD2
0x37 INT0n stuck at '1' PINT1n EPF6024 / P89C51RD2
0x38 Problem accessing NW701 registers HAD[7:0]|DV_Asn/RWn/DSUn/DSLn EPF6024 / NW701
0x39 Reset line to NW701 not functioning DV_RSTn EPF6024 / NW701
0x3A Checksum of codespace 0x0000-0xfbff is not 0x00 Incorrectly programmed P89C51RD2
0xF4 PHY chip not responding - Phy
0xF5 LINK chip not responding - Phy