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Circuit Descriptions, List of Abbreviations, and IC Data

EN 55

DVD 620 /0X1

Slave Processor Interface

Figure 9-5

The block diagram above, illustrates the interfaces of the slave
uP. The start-up sequence is as follows:
1.

The required IC voltage is the +5VSTBY, which is present
during Standby Mode.

When the RESET circuit (7320) is triggered by the
+5VSTBY, the slave uP initialises.

This will set the STDBY_CTRL signal to LOW, which will
switch on the +3V3 and +5V.

Once these voltages are provided, the host uP (STi5580 on
the SD4.0 mono board) will reset.

Now, the host uP will initialise, and indicate the slave uP to
activate the Standby Mode (STBY_CTRL) signal.

The player wakes up from the Standby Mode when any
button is pressed on the front panel, or when the 'Power'
button is pressed on the Remote Control.

Note: The slave uP will not reset successfully if the 8MHz clock
oscillator has not stabilised (check on pin 14 of item 7300).

Video Path
The video output from the STi5580 is RGB and CVBS. These
signals enter the motherboard via connector 1100.
Buffering is already done on the SD4.0 mono board, therefore
the RGB signals go directly to the SCART connector. The
CVBS signal however, first goes through a transistor (item
7132) for impedance matching.

The '0|6|12' switch signal on pin 10 of the SCART connector,
depends on the logic state of two other signals: SCART0 from
the host uP and STBY_CTRL from the slave uP. This is done
according to the following table:

Status Truth Table

Figure 9-6

Audio Path

Audio DAC circuitry

Figure 9-7

The STi5580 supplies I2S data and PCM_CLK master clock to
the new audio DAC (item 7200, AK4382AVT).
The decoded analogue output of both left and right channel is
balanced. These are filtered (3-pole LPF) and amplified with
OpAmp LM833 (item 7210). The gain of this OpAmp is two
times.
There is only one stereo output from the motherboard and a
coaxial output.

The audio DAC accepts only +5V inputs with +3V3 tolerance.
During STDBY mode, there will be no power to the audio DAC.
The registers of the audio DAC are in their default values each
time the power to the IC is cut-off. The slave uP is required to
program the DAC each time after exiting from STDBY mode.
This requires three signal lines.
•

CSN - Chip Select Pin.

•

CCLK - Control Clk Input Pin.

•

CDTI - Control Data Input Pin in Serial Mode.

CCLK and CDTI are also used as SIO_CLK and SIO_DATA
respectively, for communication between the slave uP and
STi5580. Both signal lines require pull-up resistors to
+5VSTDBY and are located in the Motherboard. Buffers for
these two signals are located in the SD4.00 Monoboard.
The host uP (STi5580) will indicate the slave uP when to
program the audio DAC after waking up from STDBY mode.

The audio MUTE signal depends on the logic state of two other
signals:
•

KILL: This signal comes from the host processor (STi5580)
and is meant to mute the outputs during switch on/off.

•

KILL_LR: This is a signal from the audio DAC, when it
receives no input for a certain time (8192 LRCK cycles). It
can be tested in STOP, PAUSE and during track changes.

The logic level for the MUTE signal is -3V < LOW < 0V and 0V
< HIGH < +3V.

Mute Truth Table

Figure 9-8

FTD Display
The slave uP drives the 7-segment FTD. It provides a negative
DC switching drive voltage. As the display consists of seven
segments, there are seven grid signals (G1-G7) controlling
each respective grid.

TMP47C416

slave

FRONT CTRL

(3 x Tact Switch)

FRONT STDBY

(1 x Tact Switch)

OPEN|CLOSE

STOP

PLAY|PAUSE

STDBY|ON

SEGMENT

GRID