Circuit Diagrams and PWB Layouts
10.
SSB: Control STI7100
1
S
Y
S
B
S
Y
S
A
TXP
TXN
RXP
RXN
REF
ATA
CLKIN
DP
DM
REF
C1A
C2A
BYTECLK
BYTECLKVALID
PACKETCLK
ERROR
BYTECLK
BYTECLKVALID
ERROR
PACKETCLK
T
S
IN1
T
S
IN1DATA
0
1
2
3
4
5
6
7
BYTECLK
BYTECLKVALID
ERROR
PACKETCLK
T
S
IN2
T
S
IN2DATA
4
5
6
7
PIO5
0
1
2
3
4
5
6
7
PIO4
0
1
2
3
4
5
TRIGGER
S
Y
S
ITRQ
T
S
IN0
T
S
IN0DATA
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
PIO1
0
1
2
3
4
5
6
7
PIO0
U
S
B
DAA
0
1
2
3
4
5
6
7
0
1
2
3
S
Y
S
BCLKO
S
C
S
Y
S
BCLKINALT
S
Y
S
CLKOUT
RTCCLKIN
TMUCLK
R
S
ETIN
WDOGR
S
TOUT
A
S
EBRK
IN
OUT
0
1
2
3
NMI
TDI
TM
S
TCK
TR
S
T
TDO
6
7
PIO
3
0
1
2
3
4
5
6
7
PIO2
1
1
1
1
1
C
1
20
H
6
7
20
19
F
2A2
3
B7
2A24 G11
2A25 G11
3
A10-1 A
8
3
A10-2 A5
3
A10-
3
A5
3
A10-4 A5
MODE[
3
:2]
PLL0
s
t
a
rt
u
p config
u
r
a
tion
O
MODE[12:11]
1
2
A
1
2
3
MODE[14]
MODE[1:0]
EMI pin
10
3
A11 H9
12
1
3
1
2
3
4
5
11
P
P
O
N
C
B
2
B
A
K
8
9
10
E
F
G
H
I
1A10 C7
E
3
A22 D
8
G
H
I
A
B
C
D
2A1
8
B2
2A19 B
3
2A20 B
3
2A21 D6
2A22 C7
17
1
8
Re
s
erved
10
11
N
M
L
3
4
5
6
7
8
9
EMIADDR[1
3
:12]
3
A
3
0-
3
F
3
3
A12 I9
3
A1
3
D9
3
A14 C
8
3
A15 D
8
3
A16 B6
3
A17 C
8
3
A1
8
B
8
P
u
rpo
s
e
3
Re
s
erved
19
1
8
17
owner.
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
11
12
1
3
A
B
C
D
3
A21 A
8
3
A
3
5 H
3
3
A2
3
C6
3
A25-1 D
8
3
A25-2 D
8
3
A25-
3
D
8
3
A25-4 D
8
3
A26 C6
3
A27 C
8
6
1
5
1
3
1
F
5
4
Re
s
erved
7
8
9
10
11
12
1
3
14
J
I
PCMOUT2
PCMOUT
3
3
A
3
0-2 F
3
9A12 E11
3
A
3
0-4 F
3
3
A
3
1-2 G
3
3
A
3
1-
3
G1
3
A
3
1-4 H
3
3
A
3
2-1 G
3
3
A
3
2-
3
H
3
3
A
33
C11
G
D
MODE[9:
8
]
FA11 C9
IA10 D9
16
15
3
A19 H1
3
A20-2 A9
3
A20-
3
A9
3
A20-4 A9
3
A
3
4 G11
IA22 D5
3
A
3
6 G
3
3
A
3
7 E11
3
A
38
E12
3
A
3
9 G9
3
A40-1 I
3
3
A40-2 H
3
5A10 A2
C
D
E
6
CONTROL
S
TI7100
EMIADDR[
8
:5]
Re
s
erved
IA2
3
C9
12
7A00-4 B10
7A10-1 B
3
3
A2
8
B
8
3
A29-1 E
3
3
A29-2 E
3
3
A29-
3
F
3
3
A29-4 F
3
3
A
3
0-1 G
3
9A11 D11
6
9A1
3
E11
9A14 F11
9A15 F11
9A20 D4
9A21 C4
9A22 B
8
FA10 C6
G
F
E
PLL1
s
t
a
rt
u
p config
u
r
a
tion
EMIADDR[15]
Long re
s
eto
u
t mode
MODE[1
3
]
H
I
J
K
IA11 D9
IA12 D9
IA1
3
D9
M
MODE[15]
S
Tx71000 m
as
ter/
s
l
a
ve mode
EMI
ba
nk
s
port
s
ize
a
t
b
oot
IA21 D4
EMIADDR[10:9]
PCMOUT4
MODE[16]
Mode pin
EMIADDR[4:
3
]
4
5
MODE[7:4]
IA24 C11
IA25 G11
7A10-2 C4
7A10-
3
C5
7A10-4 C2
7A10-5 D
3
7A10-6 D
3
7A12 D4
9A10 D11
7
IA26 G11
IA27 G11
IA2
8
C9
IA29 C5
IA
3
0 H10
IA
3
1 I10
9
8
MODE[10]
EMIADDR[14]
Re
s
erved
RE
S
IA14 D9
IA15 C9
IA16 B
8
IA17 C4
IA1
8
B7
IA19 A
3
IA20 C7
L
14
EMIADDR[2:1]
3
6
9A1
3
3
A
3
2-
3
10K
1n0
2A20
3
A
33
1K5
IA17
IA1
3
IA12
10K
3
A20-4
45
3
A27
1M0
3
A10-2
10K
10K
3
A
38
RE
S
3
A19
10K
9A12
RE
S
2A25
10n
+
3
V
3
IA
3
0
IA
3
1
3
A25-
3
10K
10K
3
A25-2
V_LVC04
10K
3
A1
8
IA26
IA16
9A22
100n
2A1
8
10K
3
A40-1
1
8
10K
2
7
4
5
3
A40-2
IA1
8
3
A
3
0-4
10K
2
7
3
A
3
0-2
10K
3
A11
47R
IA15
+
3
V
3
IA2
3
10n
2A24
3
7
14
4
9A14
7A10-2
74LVCU04APW
3
6
FA10
3
A20-
3
10K
10K
3
A22
220R
5A10
+
3
V
3
9A10
2
1
4
3
7A12
27M
2560TK
+
3
V
3
9A20
7A10-
3
74LVCU04APW
5
71
4
6
9A21
RE
S
+
3
V
3
9
71
4
8
AP25
AN25
AM25
E19
74LVCU04APW
7A10-4
AP1
AN2
AN1
AM2
AM1
AL2
AL1
AL
3
AP2
AP
3
AD4
AD5
AC4
AC5
AB4
AB5
AA4
AE4
AF4
AM
3
AN
3
AK1
AK2
AJ1
AJ2
AH1
AH2
AH4
AJ4
AG5
AF5
AE5
D22
E22
E21
E1
8
D17
D1
8
AK6
AJ5
AH5
AG4
D16
C1
AP27
E27
AN27
E17
AK25
AK26
AK27
AK2
8
D21
AB
3
0
AB
3
1
AA
3
0
AB
33
AA
3
4
AA
33
Y
3
4
Y
33
AA
3
1
Y
3
0
Y
3
1
AD
3
4
AD
33
AC
3
4
AC
33
AB
3
4
AD
3
2
AD
3
0
AD
3
1
AC
3
0
AC
3
1
AJ
3
0
AJ
3
1
AH
3
0
AH
3
1
AG
3
0
AG
3
1
AE
3
1
AE
3
0
AE
3
2
AE
3
4
AE
33
AM
33
AM
3
4
AL
3
2
AL
3
4
AL
33
AK
3
4
AK
33
AJ
3
4
AJ
33
AH
3
4
AH
33
AP5
E16
E20
D19
D20
AM
3
2
AP
33
AN
33
AP
3
4
AN
3
4
DIGITAL
INTERFACE
AM
3
0
AP
3
1
AN
3
1
AP
3
0
AN
3
0
AN5
7A00-4
S
TI7100YWC
Φ
3
A2
8
560R
V_LVC04
V_LVC04
9A11
47R
3
A2
3
V_LVC04
2
7
+
3
V
3
10K
3
A
3
1-2
3
A1
3
10K
2A22
1
8
p
1
8
p
2A2
3
3
A15
10K
+
3
V
3
10K
3
A17
IA21
IA22
100R
3
A
3
7
10K
IA27
3
A
3
1-
3
3
A25-1
10K
FA11
3
A29-2
2
7
10K
10K
3
A
3
0-
3
3
6
IA11
IA25
27M
IA29
1A10
IA2
8
10K
3
A
3
5
10K
3
A
3
9
10K
3
A25-4
1
8
+2V6-MP4
3
A
3
2-1
10K
7A10-6
74LVCU04APW
1
3
71
4
12
4
5
10K
3
A10-1
10K
3
A
3
1-4
3
A10-
3
10K
27
3
A20-2
10K
470R
3
A
3
4
IA14
3
A12
47R
3
A
3
6
10K
1
8
8
10K
3
A
3
0-1
3
A29-1
10K
1
10K
3
A29-4
4
5
74LVCU04APW
11
71
4
10
7A10-5
IA24
2A19
100n
3
A10-4
10K
10K
3
A29-
3
3
6
9A15
IA10
200
8
-04-25
DC
3
07
3
67
YiPing G
u
o
200
8
-04-1
8
3
10K
3
A21
A2
PB522
PCB
S
B PB522 He
a
lthc
a
re
3
1
3
9 2
83
3
00
3
CHECK
DATE
NAME
1
S
UPER
S
.
CLA
SS
_NO
2
2
5
B
P
E
M
A
N
T
E
S
N
H
C
4
3
3
PC
33
2
3
4
200
8
-02-2
8
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 2007
IA20
1
3
0
IA19
3
A26
6
8
R
3
A16
10K
1
71
4
2
74LVCU04APW
7A10-1
3
A14
22R
2A21
15p
27MHZ-
3
V
3
CPU-27MHZ
TMUCLK
CPU-notRE
S
ET
RE
S
ET-
S
T7101
JTAG-TR
S
Tn
CPU-27MHZ
TRIG-IN
EMI-A(14)
PCMOUT2
PCMOUT
3
WP-FLA
S
H-
S
T
CPU-I2C-
S
DA
S
CL-
SS
B
CPU-I2C-
S
CL
EMI-A(6)
EMI-A(5)
EMI-A(10)
EMI-A(9)
PCMOUT4
EMI-A(1
3
)
EMI-A(12)
EMI-A(14)
EMI-A(15)
EMI-A(4)
EMI-A(1)
EMI-A(2)
CPU-I2C-
S
CL
CPU-I2C-
S
DA
PDRX-DDC-
S
CL
PDRX-DDC-
S
DA
S
DA-
SS
B
27MHZ-
3
V
3
A
S
EBRKn
TRIG-OUT
RXD-A
S
C2
TXD-A
S
C2
JTAG-TDI
JTAG-TM
S
JTAG-TCK
JTAG-TDO
EMI-A(
3
)
EMI-A(
8
)
EMI-A(7)
FE-DATA1
FE-DATA2
FE-DATA
3
FE-DATA4
FE-DATA5
FE-DATA6
FE-DATA7
FE-
S
OP
CPU-I2C-
S
CL
CPU-I2C-
S
DA
CLK_REF
DVID0
DVID1
DVID2
DVID
3
DVID4
DVID5
DVID6
DVID7
TXD-A
S
C
3
RXD-A
S
C
3
JTAG-TCK
JTAG-TDI
JTAG-TDO
JTAG-TM
S
FE-CLK
FE-VALID
FE-DATA0
1
8
710_5
33
_090
8
24.ep
s
090
8
24