Circuit Diagrams and PWB Layouts
10.
SSB: FPGA 1080p: Power & Control
DATA
GND
A
S
DI
DCLK
C
S
_
VCC
OUT
IN
INH
BP
COM
COM
OUT
IN
COM
OUT
IN
F
H
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
I
C
B
1
2
3
4
12
11
10
8
9
E
G
1
2
5
6
7
E
D
D
A
owner.
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
5
6
7
FPGA 10
8
0p : POWER + CONTROL
3
4
5
6
1
2
3
4
7
8
9
8
9
A
B
D
E
A
C
B
C
IFA7
2FE2
10n
10n
2FE6
1K0
1K0
3
FA4
3
FB9
FFA4
3
FC7
100K
IFA2
FFA
3
IFA6
3
0R
5FA7
FFAA
CLA
SS
_NO
2
2
5
B
P
E
M
A
N
T
E
S
N
H
C
3
PC
3
22
DC
3
07
3
67
PB522
+1V2-
S
TAB
100n
2FA5
2FA0
1
u
0
4
2
1
3
5
+
3
V
3
7FA4
LD
3
9
8
5M25
100R
3
FA7
3
FA6
100R
25V
220
u
2FC0
2FF6
S
TP
S
2L
3
0A
6FA6
10n
2FD
3
10n
IFA1
2FA2
5FA1
3
0R
10n
5FB2
220R
2FE4
10n
3
FB2
100n
2FK
8
2FE5
10K
10n
IFA9
5
1
2
6
4
3
7
8
1112
Φ
S
CD
7FA
3
EPC
S
4
S
I
8
1FA0
1
10
2
3
4
5
6
7
8
9
IFA
3
2FA
3
10n
+
3
V
3
9FA1
9FA2
100K
3
FC
8
2FD5
10n
S
ML-
3
10
6FA0
2FD1
10n
2FB7
10n
10n
2FE1
2FA9
4
u
7
10n
2FB2
10K
+
3
V
3
-FPGA
3
FA1
2
BC
8
47BW
7FA0
1
3
IFB2
+2V5-
S
TAB
+
3
V
3
2FA7
10n
2FF0
1
u
0
FFA0
10n
2FB5
FFB1
3
0R
5FA
8
10n
2FF
3
FFA2
+1V2-
S
TAB
FFA
8
2FD2
10n
100K
3
FA2
10n
2FA4
10n
2FF4
LD1117DT12
1
3
2
2FB1
10n
7FA5
+2V5
10n
+
3
V
3
2FF7
6FA7
S
TP
S
2L
3
0A
3
FC6
100K
1
3
2
LD1117DT25
7FK1
BC
8
47BW
7FA1
10n
2FD4
220R
5FB1
FFB2
2FD0
7
u
4
0
u
1
2FB9
10n
2FB
3
FFA7
220R
5FA2
2FC1
1
u
0
IFB
3
2FE7
10n
2FF2
10n
FFA5
FFA9
10n
2FE
3
10n
2FD9
+2V5-
S
TAB
2FK7
100
u
16V
1
u
0
2FA6
FFA6
10n
3
K
3
3
FA0
2FA1
+
3
V
3
-FPGA
2FB0
1
u
0
2FE0
4
u
7
10n
2FD7
100R
3
FB
8
2FA
8
100n
1K0
3
FA5
1K0
3
FA
3
RE
S
2FD6
10n
2FF1
10n
3
FA
8
100R
FFB0
2FD
8
10n
2FB6
10n
2FC2
1
u
0
RE
S
2FF5
22
u
FFA1
IFB1
5FA6
3
0R
10n
2FB4
+Vin-FPGA
DATA0
+
3
V
3
+
3
V
3
+1V2-FPGA
A
S
DO
nC
S
O
DCLK
nCONFIG
+
3
V
3
-FPGA
ON-MODE
+
3
V
3
-FPGA
+
3
V
3
CONF-DONE
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TM
S
+
3
V
3
-FPGA
+
3
V
3
-FPGA
+
3
V
3
-FPGA
+2V5o
u
t-FPGA
+1V2-PLL