Circuit Diagrams and PWB Layouts
10.
Digital Bolt-On: Clock, EEPROM, JTAG & BBS
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
3
OT_XTAL_P
3
OT_XTAL_N
EJT_TDI
EJT_TR
S
T_N
EJT_TCK
EJT_TM
S
D
3
.
3
V
D
3
.
3
V_BCM740X
CLK27_CLK
33 8
Clock, EEPROM, JTAG & BB
S
"BB
S
"
EJTAG
HP51
HP51
R167
22
R167
22
R175
*
2.7K
R175
*
2.7K
Y1
D/54MHz
Y1
D/54MHz
R165
3
01/1
%
R165
3
01/1
%
R17
3
*
2.7K
R17
3
*
2.7K
TP5
TP5
C1
3
4
12p
C1
3
4
12p
IR_IN0
AF1
8
IR_OUT
A22
IR_IN1/RMX_PAU
S
E1/RMXP_PAU
S
E
AF20
Infr
a
red
U1-10
BCM7402
Infr
a
red
U1-10
BCM7402
HP112
HP112
R166
3
01/1
%
R166
3
01/1
%
HP5
3
HP5
3
1
2
3
4
5
6
7
8
RN
88
1K
RN
88
1K
HP50
HP50
R172
*
2.7K
R172
*
2.7K
HP
3
4
HP
3
4
R164
22
R164
22
R169
*
0
R169
*
0
HP
3
5
HP
3
5
BYP_
S
Y
S
9_CLK
T20
CLK54_XTALP
C26
CLK54_XTALN
D26
CLK27_OUT/CLK_
33
V22
EXT_DDR0_CLK
B
3
VCXO27A
AF14
BYP_RFM_PLLO
F19
BYP_CPU_CLK
U20
OB
S
RV_PLL
R20
OB
S
RV_VCXO
V21
BYP_AVD_CLK
Y9
BYP_AUD_D
S
P_CLK
H14
Clock
s
U1-12
BCM7402
Clock
s
U1-12
BCM7402
HP49
HP49
C1
3
5
12p
C1
3
5
12p
TMODE_0
Y11
TMODE_1
Y12
TMODE_2
Y14
B
S
C_
S
_
S
CL/
S
PI_
S
_
S
CK
E24
B
S
C_
S
_
S
DA/
S
PI_
S
_MO
S
I
F24
EJTAG_TR
S
T
b
W22
EJTAG_TDI/OB
S
RV_PLL_
S
EL1
Y26
EJTAG_TDO
W2
3
EJTAG_TM
S
/OB
S
RV_PLL_
S
EL2
W25
EJTAG_TCK/OB
S
RV_PLL_
S
EL0
W24
TMODE_
3
Y1
3
TE
S
T
Bro
a
dB
a
nd
S
t
u
dio
U1-
8
BCM7402
TE
S
T
Bro
a
dB
a
nd
S
t
u
dio
U1-
8
BCM7402
HP
3
6
HP
3
6
R161
33
R161
33
HP52
HP52
HP
38
HP
38
C1
3
2
15p
C1
3
2
15p
R176
*
2.7K
R176
*
2.7K
UHF_IN_P
A24
UHF_IN_N
B24
UHF_IFI
B25
RFM_DAC0_p
B20
RFM_DAC0_n
A20
RFM_RBIA
S
_DAC0
D20
RFM_BIA
S
_REF
C20
UHF_IFO
A26
An
a
log I/O
U1-14
BCM7402
An
a
log I/O
U1-14
BCM7402
R162
0
R162
0
R16
3
*33
R16
3
*33
R170
*
0
R170
*
0
L12
FB/2.7
u
/0
8
L12
FB/2.7
u
/0
8
C1
3
1
15p
C1
3
1
15p
1
8
610_507_090605.ep
s
090605