Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.11 IC Data Sheets
This section shows the internal block diagrams and pin layouts
of ICs that are drawn as "black boxes" in the electrical diagrams
(with the exception of "memory" and "logic" ICs).
9.11.1 Diagram B2, Type TDA15021H (IC7217, Hercules)
Figure 9-8 Internal block diagram and pin configuration
E
V
I
R
D
-
V
D
W
E
O
T
H
E
F
I
D
N
U
O
S
S
S
Q
C
G
A
R
E
X
I
M
S
S
Q
R
O
T
A
L
U
D
O
M
E
D
M
A
C
F
A
/
C
G
A
/
F
I
N
O
I
S
I
V
.
D
O
M
E
D
L
L
P
.
P
M
A
O
E
D
I
V
P
A
R
T
D
N
U
O
S
Y
A
L
E
D
P
U
O
R
G
H
C
T
I
W
S
O
E
D
I
V
.
T
N
E
D
I
O
E
D
I
V
S
R
E
T
L
I
F
O
E
D
I
V
H
4
/
H
2
R
E
T
L
I
F
B
M
O
C
R
E
D
O
C
E
D
C
S
T
N
/
M
A
C
E
S
/
L
A
P
D
N
A
B
-
E
S
A
B
E
N
I
L
Y
A
L
E
D
.
P
E
S
C
N
Y
S
V
/
H
L
L
P
+
.
C
S
O
-
H
2
d
n
P
O
O
L
T
F
I
H
S
-
H
E
V
I
R
D
-
H
L
A
C
I
T
R
E
V
Y
R
T
E
M
O
E
G
T
S
E
W
-
T
S
A
E
&
N
I
B
V
D
/
N
I
F
I
S
T
U
O
C
G
A
N
I
F
I
V
3
Y
/
3
S
B
V
C
3
C
/
2
C
4
Y
/
4
S
B
V
C
4
C
/
O
S
B
V
C
F
I
S
S
T
U
O
H
G
N
I
K
A
E
P
Y
T
I
C
O
L
E
V
N
A
C
S
P
Y
/
B
G
R
R
P
B
T
R
E
S
N
I
E
C
A
F
R
E
T
N
I
V
U
Y
.
N
O
C
I
R
B
T
A
S
L
O
R
T
N
O
C
A
M
M
A
G
H
C
T
E
R
T
S
K
C
A
L
B
μ
R
E
D
O
C
E
D
T
X
E
T
E
L
E
T
D
N
A
R
O
S
S
E
C
O
R
P
-
R
C
B
G
R
L
B
O
R
O
G
O
B
N
I
L
C
B
N
I
K
L
B
L
O
R
T
N
O
C
B
G
R
T
R
E
S
N
I
T
X
E
T
/
D
S
O
C
C
C
.
J
D
A
.
P
-
E
T
I
H
W
N
T
H
G
I
R
B
/
R
T
N
O
C
X
I
R
T
A
M
B
G
R
P
S
D
o
i
d
u
a
h
t
i
w
r
o
s
s
e
c
o
r
p
V
T
”
o
e
r
e
t
s
-
V
A
“
e
h
t
f
o
m
a
r
g
a
i
d
k
c
o
l
B
M
V
S
s
O
/
I
C
Y
V
/
H
O
R
M
F
/
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B
V
D
H
C
T
I
W
S
O
F
E
R
F
E
R
.
J
D
A
Y
A
L
E
D
Y
M
E
V
A
C
S
T
X
E
T
N
O
E
N
O
T
N
I
K
S
T
N
I
T
V
/
U
Y
A
L
E
D
V
/
U
N
O
I
T
A
R
U
T
A
S
N
O
I
T
A
L
U
D
O
M
H
C
T
E
R
T
S
E
U
L
B
2
Y
/
2
S
B
V
C
/
O
V
S
/
O
V
F
I
C
N
Y
S
Y
YU
V
IN/OUT
M
A
T
U
O
M
A
/
O
S
S
Q
/
O
V
F
I
/
O
B
V
D
L
L
P
D
N
U
O
S
S
I
S
A
H
P
M
E
E
D
S
E
R
U
T
A
E
F
G
N
I
S
S
E
C
O
R
P
L
A
N
G
I
S
L
A
T
I
G
I
D
L
B
Y
/
G
P
/
R
R
P
/
B
B
1
O
W
S
L
B
Y
/
G
P
/
B
B
o
U
o
V
o
Y
i
Y
i
U
i
V
)
x
C
(
)
x
Y
/
x
S
B
V
C
(
P
/
R
R
P
I
P
I
S
B
V
C
S
D
R
T
C
E
L
E
S
O
I
D
U
A
T
U
O
/
N
I
H
C
N
I
C
/
T
R
A
C
S
S
2
I
T
U
O
-
S
L
L
R
L
O
R
T
N
O
C
O
I
D
U
A
E
M
U
L
O
V
S
S
A
B
/
E
L
B
B
E
R
T
S
E
R
U
T
A
E
F
C
A
D
/
C
D
A
s
C
A
D
R
L
T
U
O
-
P
H
O
R
M
F
L
A
T
I
G
I
D
Pin config
u
ration “stereo” and “A
V
-stereo” versions with A
u
dio DSP
69
70
81
80
79
78
77
76
75
74
73
72
71
88
87
86
85
84
83
82
65
66
68
67
89
96
95
94
93
92
91
90
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9
10
11
12
29
31
32
30
5
6
7
8
1
2
3
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
4
1
5
2
5
3
5
4
5
6
5
5
5
3
3
4
3
5
3
6
3
7
3
8
3
9
3
0
4
7
5
8
5
9
5
0
6
1
6
2
6
4
6
3
6
0
5
QFP-128 0.8 mm pitch “face down version”
A
D
N
G
2
1
1
1
1
1
0
1
1
9
0
1
8
0
1
7
0
1
6
0
1
5
0
1
3
1
1
4
1
1
5
1
1
6
1
1
7
1
1
8
1
1
9
1
1
0
2
1
1
2
1
2
2
1
3
2
1
4
2
1
5
2
1
6
2
1
7
2
1
8
2
1
4
0
1
3
0
1
2
0
1
1
0
1
0
0
1
9
9
8
9
7
9
P0.1/I2SDO1
P0.2/I2SDO2
P0.0/I2SDI1
V
SSC2
P0.3/I2SCLK
P0.4/I2SWS
V
DDC2
V
SSC3
)
V
3.
3(
3
A
D
D
V
)
V
8.
1(
A
D
D
V
V
DDC3
P3.2/ADC2
P3.3/ADC3
V
SSC1/P
INT0/P0.5
P3.0/ADC0
P3.1/ADC1
P2.3/PWM2
P1.6/SCL
P2.2/PWM1
P2.1/PWM0
P2.0/PMW
P1.7/SDA
P1.3/T1
P2.4/PWM3
V
DDP(3.3
V
)
V
DDC1(1.8)
L
S
L
_
S
O
P
_
F
E
R
V
)
V
3.
3(
2
A
D
D
V
P1.2/INT2
A
R
D
V
1
NI
FI
V
2
NI
FI
V
C
S
V
L
L
P
C
E
S
GI
D
C
E
D
F
L
1
H
P
G
B
C
E
D
D
W
E/
L
V
A
B
R
D
V
F
E
RI
T
U
O
C
G
A
1
NI
FI
S/
1
NI
B
V
D
2
NI
FI
S/
2
NI
B
V
D
P1.4/RX
1
P
V
NI
L
A
T
X
T
U
O
L
A
T
X
1
A
S
S
V
FI
D
N
G
L
P
H
+
R
S
L
_
S
O
P
_
F
E
R
V
R
P
H
+
L
P
H
_
G
E
N
_
F
E
R
V
R
P
H
_
S
O
P
_
F
E
R
V
R
S
L
+
L
S
L
_
G
E
N
_
F
E
R
V
Y
S
C/
O
SI
B
F
C
V
BSO/PIP
AUDIOIN5L
M
V
S
GND2
D
V
BO//IF
V
O/FMRO
D
V
BO/FMRO
AGC2SIF
AUDIOIN4L
SIFAGC/D
V
BAGC
PLLIF
AUDIOIN5R
AUDOUTLSL
AUDOUTLSR
AUDIOIN4R
V
CC8
V
C
V
BS3/Y3
AUDIOIN2L/SSIF
AUDIOIN2R
C
V
BS4/Y4
AUDIOIN3L
AUDIOIN3R
C4
AUDOUTHPL
AUDOUTHPR
C
V
BS2/Y2
V
P2
S
V
O/IFOUT/C
V
BSI
C2/C3
DECSDEM
AMOUT/QSSO/AUDEEM
O
T
H
E
b
m
o
c
D
D
V
).
V
3.
3(
1
A
D
D
V
O
B
O
G
O
R
G
E
N
_
D
A
F
E
R
V
T
U
O
H
S
O
P
_
D
A
F
E
R
V
b
m
o
c
S
S
V
3
W
S
S
NI
P/
R
R
3-
NI
K
L
B
NI
L
C
B
P/
B
B
3-
3-
Y/
G
)
X-
Y/
S
B
V
C/
2-
Y/
G(
NI
Y
)
1
O
W
S(
T
U
O
V
)
2-
W
S
NI
(
T
U
O
U
T
U
O
Y
NI
U
P/
R(
NI
V
R
)
X-
C/
2-
P/
B(
B
)
2-
C
N
Y
S
Y
3
P
V
3
D
N
G
D
A
F
E
R
V
P1.O/INT1
P1.1/T0
)
8.
1(
c
d
a
D
D
V
c
d
a
S
S
V
REFIN/REFOUT
OI
W
S/
D
R
A
U
G
V
P2.5/PWM4
DEC
V
1
V
8
1
D
N
G
AUDOUTSL
AUDOUTSR
P1.5/TX
4
C
D
D
V
4
C
S
S
V
2
P
S
S
V
A
V
L/SWO/SSIF/
F
L
2
H
P
E_14490_063.eps
240505
Block Diagram
Pin Configuration