Philips 22HFL5662H/F7, Руководство по обслуживанию

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Circuit Diagrams and PWB Layouts EN 67 TPB1.2HU LA 10.
2011-Mar-11
SMB: LVDS to DVO
1 888 0_5 3 1_10100 8 .ep s
10100 8
LVD S to DVO
B1 8
2010-05-14 0.4
BUH NAFTA 2k10 v0.4
017G MB 4 ZW
LVD S to DVO
B1 8
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVD S _TX_0_DATA4_P
LVD S _TX_1_CLK_P
LVD S _TX_1_DATA 3 _P
LVD S _TX_1_DATA1_P
LVD S _TX_1_DATA0_N
LVD S _TX_1_DATA1_N
LVD S _TX_1_DATA 3 _N
LVD S _TX_1_CLK_N
LVD S _TX_1_DATA4_P
LVD S _TX_1_DATA4_N
LVD S _TX_1_DATA2_N
LVD S _TX_1_DATA2_P
LVD S _TX_1_DATA0_P
LVD S _TX_0_DATA 3 _N
LVD S _TX_0_DATA 3 _P
LVD S _TX_0_DATA2_P
LVD S _TX_0_CLK_N
LVD S _TX_0_DATA1_N
LVD S _TX_0_DATA0_N
LVD S _TX_0_CLK_P
LVD S _TX_0_DATA4_N
LVD S _TX_0_DATA1_P
LVD S _TX_0_DATA0_P
LVD S _TX_0_DATA2_N
GOUT1 8
GOUT19
BOUT19
GOUT11
GOUT12
GOUT1
3
GOUT14
GOUT16
GOUT15
GOUT10
ROUT1 8
ROUT19
M1_B15
B10
R19
LVD S _TX_0_DATA4_N
LVD S _TX_0_DATA4_P
M2_B16
G11
GOUT17
R12
LVD S _TX_0_CLK_P
LVD S _TX_0_CLK_N
B11
PROG_B
LVD S _TX_0_DATA2_N
LVD S _TX_0_DATA2_P
G12
R1 3
B12
LVD S _TX_0_DATA 3 _P
LVD S _TX_0_DATA 3 _N
V S 1_B19
V S 2_B1 8
V S 0_G10
CCLK
MO S I
DIN
C S O_B
G1 3
B1 3
CLK_TX_M0 CLK_TX
R14
TM S
TDI
TDO
TCK
G17
B14
G14
C S O_B
R15
INIT_B
G1 8
DONE
MO S I
G15
LVD S _TX_1_DATA4_N
LVD S _TX_1_DATA4_P
BOUT1 8
BOUT17
R16
DIN
TCK
V S 0_G10
V S 1_B19
G19
LVD S _TX_1_DATA 3 _N
LVD S _TX_1_DATA 3 _P
CCLK
TDO
G16
TDI
LVD S _TX_1_DATA2_P
LVD S _TX_1_DATA2_N
ROUT10
ROUT11
ROUT1 3
ROUT12
R10
TM S
V S _TX
CCLK
LVD S _TX_1_DATA1_N
LVD S _TX_1_DATA1_P
ROUT14
ROUT16
ROUT17
BOUT1 3
BOUT10
BOUT12
BOUT11
V S 2_B1 8
BOUT14
MO S I
C S O_B
R17
DIN
B17
LVD S _TX_1_DATA0_N
LVD S _TX_1_DATA0_P
R11
H S _TX
CLK_TX_M0
R1 8
DE_TX
CLK_TX_M0
BOUT15
BOUT16
M2_B16
M1_B15
ROUT15
LVD S _TX_0_DATA1_N
LVD S _TX_0_DATA0_P
LVD S _TX_0_DATA1_P
LVD S _TX_0_DATA0_N
3 . 3 V_Active
3 . 3 V_Active
3 . 3 V_Active
3 . 3 V_Active
3 . 3 V_Active
3 . 3 V_Active
3 . 3 V_Active
D1.2V
GOUT1 8 [21]
GOUT19 [21]
BOUT19 [21]
GOUT11 [21]
GOUT12 [21]
GOUT1 3 [21]
GOUT14 [21]
GOUT15 [21]
GOUT16 [21]
GOUT10 [21]
ROUT19 [21]
ROUT1 8 [21]
GOUT17 [21]
DVO_V S YNC_TX [21]
DVO_H S YNC_TX [21]
DVO_DE_TX [21]
DVO_CLK_TX [21]
BOUT1 8 [21]
BOUT17 [21]
FPGA_R S T [12]
ROUT10 [21]
ROUT11 [21]
ROUT12 [21]
ROUT1 3 [21]
ROUT14 [21]
ROUT15 [21]
ROUT16 [21]
ROUT17 [21]
BOUT1 3 [21]
BOUT10 [21]
BOUT11 [21]
BOUT12 [21]
BOUT14 [21]
BOUT15 [21]
BOUT16 [21]
PROG_B [12]
GP5 3 _GPIO [12]
GP54_GPIO [12]
GP55_GPIO [12]
RN40 22 RN40 22
1
2
3
4 5
6
7
8
J19
* HEADER 1x6 PH2.54mm
J19
* HEADER 1x6 PH2.54mm
1
2
3
4
5
6
C44 3 0.1 u F C44 3 0.1 u F
C447
0.1
u F
C447
0.1
u F
FLA S H
U40-1
MX25L4005
FLA S H
U40-1
MX25L4005
RN 38 22 RN 38 22
1
2
3
4 5
6
7
8
LVD S
U1E
BCM
3 549L
BGA704_ S KT_ S MTBG_BCM 3 556
LVD S
U1E
BCM
3 549L
BGA704_ S KT_ S MTBG_BCM 3 556
LVD S _TX_0_DATA0_N
A4
LVD S _TX_0_DATA0_P
B4
LVD S _TX_0_DATA1_N
B6
LVD S _TX_0_DATA1_P
C6
LVD S _TX_0_DATA2_N
A 3
LVD S _TX_0_DATA2_P
B 3
LVD S _TX_0_DATA 3 _N
A2
LVD S _TX_0_DATA 3 _P
A1
LVD S _TX_0_DATA4_N
D6
LVD S _TX_0_DATA4_P
D5
LVD S _TX_0_CLK_N
B5
LVD S _TX_0_CLK_P
C5
LVD S _TX_1_DATA0_N
B2
LVD S _TX_1_DATA0_P
B1
LVD S _TX_1_DATA1_N
C 3
LVD S _TX_1_DATA1_P
C2
LVD S _TX_1_DATA2_N
D2
LVD S _TX_1_DATA2_P
D1
LVD S _TX_1_DATA 3 _N
E2
LVD S _TX_1_DATA 3 _P
E1
LVD S _TX_1_DATA4_N
E4
LVD S _TX_1_DATA4_P
E 3
LVD S _TX_1_CLK_N
D4
LVD S _TX_1_CLK_P
D 3
J21
HEADER 1x6 PH2.54mm
J21
HEADER 1x6 PH2.54mm
1
2
3
4
5
6
C445 0.1 u F C445 0.1 u F
C4 3 4 0.1 u F C4 3 4 0.1 u F
RD27 1K RD27 1K
1 3
2
R 3 15
* 4.7K
R 3 15
* 4.7K
C446 0.1 u F C446 0.1 u F
RN 3 5 22 RN 3 5 22
1
2
3
4 5
6
7
8
C440 0.1 u F C440 0.1 u F
R 3 16 22 R 3 16 22
RD2 3 33 0 RD2 3 33 0
1 3
2
RN 3 6 22 RN 3 6 22
1
2
3
4 5
6
7
8
J20
PIN HEADER 1X2 2.54
J20
PIN HEADER 1X2 2.54
1
2
C4 3 6 0.1 u F C4 3 6 0.1 u F
R 3 17
4.7K
R 3 17
4.7K
RD24 33 0 RD24 33 0
1 3
2
RN 3 9 22 RN 3 9 22
1
2
3
4 5
6
7
8
U40
MX25L4005AM2C-12G U40
MX25L4005AM2C-12G
C S
1
S O
2
WP
3
GND
4
VCC
8
NC
7
S CK
6
S I
5
RN 3 7 22 RN 3 7 22
1
2
3
4 5
6
7
8
C442 0.1 u F C442 0.1 u F
C4 33
10pF
C4 33
10pF
C4 3 5 0.1 u F C4 3 5 0.1 u F
U 3 9
FPGA
U 3 9
FPGA
TM S
1
TDI
2
IO_L01P_ 3
3
IO_L01N_ 3
4
IO_L02P_ 3
5
IO_L02N_ 3
6
IP_ 3 /VREF_ 3
7
GND
8
IO_L0 3 P_ 3 /LHCLK0
9
IO_L0 3 N_ 3 /LHCLK1
10
VCCO_ 3
11
IO_L04P_ 3 /LHCLK2
12
IO_L04N_ 3 /IRDY2/LHCLK 3
1 3
GND
14
IO_L05P_ 3 /TRDY2/LHCLK6
15
IO_L05N_ 3 /LHCLK7
16
VCCINT
17
GND
1 8
IO_L06P_ 3
19
IO_L06N_ 3
20
IP_ 3
21
VCCAUX
22
IO_L01P_2/M1
2 3
IO_L02P_2/M2
24
IO_L01N_2/M0
25
VCCO_2
26
IO_L02N_2/C S O_B
27
IO_L0 3 P_2/RDWR_B
2 8
IO_L04P_2/V S 2
29
IO_L0 3 N_2/V S 1
3 0
IO_L04N_2/V S 0
3 1
IO_L05P_2
3 2
IO_L06P_2
33
IO_L05N_2/D7
3 4
IO_L06N_2/D6
3 5
IO_L07P_2/D5
3 6
IO_L07N_2/D4
3 7
VCCINT
38
IP_2/VREF_2
3 9
IO_L0 8 P_2/GCLK14
40
IO_L0 8 N_2/GCLK15
41
GND
42
IO_L09P_2/GCLK0
4 3
IO_L09N_2/GCLK1
44
VCCO_2
45
IO_2/MO S I/C S I_B
46
GND
47
IO_L10P_2/INIT_B
4 8
IO_L10N_2/D 3
49
IO_L11P_2/D2
50
IO_L11N_2/D0/DIN/MI S O
51
IO_L12P_2/D1
52
IO_L12N_2/CCLK
5 3
DONE
54
VCCAUX
55
IO_L01P_1
56
IO_L01N_1
57
GND
5 8
IO_L02P_1/RHCLK0
59
IO_L02N_1/RHCLK1
60
IO_L0 3 P_1/RHCLK2
61
IO_L0 3 N_1/TRDY1/RHCLK 3
62
GND
6 3
IO_L04P_1/IRDY1/RHCLK6
64
IO_L04N_1/RHCLK7
65
VCCINT
66
VCCO_1
67
IP_1/VREF_1
6 8
GND
69
IO_L05P_1
70
IO_L05N_1
71
IO_L06P_1
72
IO_L06N_1
7 3
GND
74
TD0
75
TCK
76
IO_L01P_0/VREF_0
77
IO_L01N_0
7 8
VCCO_0
79
GND
8 0
VCCINT
8 1
IP_0/VREF_0
8 2
IO_L02P_0/GCLK4
83
IO_L02N_0/GCLK5
8 4
IO_L0 3 P_0/GCLK6
8 5
IO_L0 3 N_0/GCLK7
8 6
GND
8 7
IO_L04P_0/GCLK 8
88
IO_L04N_0/GCLK9
8 9
IO_0/GCLK11
90
GND
91
VCCAUX
92
IO_L05P_0
9 3
IO_L05N_0
94
GND
95
VCCO_0
96
IP_0
97
IO_L06P_0/VREF_0
9 8
IO_L06N_0/PUDC_B
99
PROG_B
100
R 3 1 8
33 0
R 3 1 8
33 0
RN 33 22 RN 33 22
1
2
3
4 5
6
7
8
C4 38 0.1 u F C4 38 0.1 u F
C4 3 7 0.1 u F C4 3 7 0.1 u F
R 3 14 22 R 3 14 22
TP122 TP122
RD25 1K RD25 1K
1 3
2
TP12 3 TP12 3
RN 3 4 22 RN 3 4 22
1
2
3
4 5
6
7
8
RD22 33 0 RD22 33 0
1 3
2
R 3 11
4.7K
R 3 11
4.7K
R 3 1 3
1K
R 3 1 3
1K
R 3 20
4.7K
R 3 20
4.7K
R 3 09
0
R 3 09
0
R 3 12 22 R 3 12 22
RD26 1K RD26 1K
1 3
2
R 3 21
4.7K
R 3 21
4.7K
C441 0.1 u F C441 0.1 u F
R 3 10 22 R 3 10 22
C444 0.1 u F C444 0.1 u F
R 3 19
4.7K
R 3 19
4.7K
C4 3 9 0.1 u F C4 3 9 0.1 u F
C4 3 2
* 0.1 u F
C4 3 2
* 0.1 u F