Page 6
Pentek Model 78741 Installation Manual
Rev.: 2.5
1.4
Model 78741 Block Diagram
The following is a simplified block diagram of the Model 78741 A/D module.
ClockGate/
PPS
TIMING
CONTROL
IN 1
RF In
RF
XFORMER
Gate In
Clk Reset In
Ref Clk In
Ref Clk Out
Sample Clk /
Reference Clk In
A/D Timing Bus
PPS In
IN 2
RF In
RF
XFORMER
12
1.8 GHz
12-BIT A/D
1.8 GHz
12-BIT A/D
Input Mux
ADC12D1800
A/D Converter
12
GA
TE/
SYN
C
ADC Acquisition Module
Interleave
PCI Express Interface
Deinterleave
32
32
DDR3
SDRAM
1 GB
DDR3
SDRAM
1 GB
32
32
DDR3
SDRAM
1 GB
DDR3
SDRAM
1 GB
48
Gigabit
Serial I/O
(option 105)
FPGA
GPIO
(option 104)
PCIe
Gen3 x8
GATEXPRESS PCIe
CONFIGURATION
MANAGER
CONFIG
FLASH
1 Gb
FPGA
Config
Bus
PCIe
Gen3 x8
VIRTEX-7 FPGA
VX330T or VX690T
DDC
PMC Baseboard/Carrier Connections
SER
TX
SER
RX
GPIO
Model 7807
PCIe Carrier
PCI Express Baseboard
P14
PMC
P16
XMC
P15
XMC
I C Port
2
Figure 1
−
1: Model 78741 Block Diagram
