GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 81 of 123
For final eye calibration, adjust Voltage Swing, SJ, and DM Amplitude until the target Eye Width
and Eye Height are achieved and then save at least 10 waveforms.
8.2
Perform Initial Tx Equalization & Tx Link Equalization Response Tests
This section describes how to set up the DUT to perform initial Tx equalization (EQ) testing (for the
add-in card only) and Tx link EQ response testing (for both the system board and add-in card).
This is to ensure that the DUT will be able to apply the correct Tx EQ preset as required along the
test.
To perform the initial Tx EQ & Tx link EQ response tests, the DUT attached to a test fixture will
basically receive data signals from a stress signal generator which is also connected to reference
clock with the DUT fixture. After data is processed, the signals will be separated to flow through
two different directions- one part of the signal will be sent back through the test fixture to the
stress signal generator for error detection while the other part will be sent to the oscilloscope for
waveforms to be captured and analyzed for target EQ values.
Note:
Refer to Sections 5.2 and 5.3 for more details on test setup requirements for the DUT.
8.2.1
Equipment Setup for Add-in Card DUT Initial Tx EQ / Tx Link EQ Response Test
The following connection diagram shows the physical setup to perform initial Tx EQ / Tx link EQ
response test for the PCIe Gen 5 add-in card DUT. This setup is using the MP1900A BERT that
includes the MU195040A SI Error Detector module and a compliant CBB test fixture for the DUT.
Note
: Use logical Lane 0 for the following test setup.
F
IGURE
53.
C
ONNECTION
D
IAGRAM FOR
PCI
E
G
EN
5
A
DD
-
IN
C
ARD
DUT
I
NITIAL
T
X
EQ
/
T
X
L
INK
EQ
R
ESPONSE
T
EST
