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PGA26E07BA-SWEVB008 Ver. 1.2 

15 

 

Table 5: Double Pulse Setting with

 

L=320uH

 

Measurement Procedures

    

1) Slew Rate dV/dT tests 

Initial steps: 

Do all the necessary connection between the evaluation board, 
components and equipment. 

 

Connect DC power 

①

 to VPN and VS of the board with 

the screw terminal block. 

 

Connect deadtime circuit to the IN_H, IN_L, VDD, EN and 
GND terminal of the board. Please note that the connection of 
dead time circuit to the IN_H and IN_L depending on low side 
test or high side test (please refer to page 11). 

 

Connect the inductor from VPN to LX for boost mode (low side test) 
or connect inductor from LX to VS for buck mode (high side test).

 

 

 

The VDD voltage must be 3.3V-5V, Isolator VDDI voltage range.  
 Fix the dead time to 100ns.  

 

Connect the dead time generator to a pulse generator.  

 

Connect DC power 

②

 to VDD/GND terminal of the board to3.3/5V. 

   Connect DC power 

③

 to AUXH+/AUXH-,  AUXL+/AUXL- terminal of  

 the board. 

 

Probe the point where you want to monitor and observe the 
waveform using oscilloscope.  

Be careful not to short  with other parts.  It  is recommended to use  a coil 
wire fixture mounted near SMA2 on the evaluation board for V

DS

 monitoring 

refer to Figure 11. 
Use an SMA to Tektronics probe adaptor as shown in Figure 12. 

 

Start-up:  

 

Set up the Dead time generator circuit with the amplitude 0-5V and having the double pulse profile as 
shown below: 

 

 

                         
     

     

Figure 13: Double Pulse

 

 

 

Again,  ensure  that  the  pulse  generated  occurs  only  in  the  burst  mode.  If  the  pulse  is  generated 
continuously, the transistor will be damaged by high current flows.  

 

Set DC power 

②

to 5V. LED will glow to indicate EN (Si8275GB Enable pin) is high  

 

Adjust DC power 

③

 to 12V gradually. 

 

Check V

GS

 waveform when a double pulse is inputted from pulse generator.  Ensure to carry out this step 

with DC power 

①

 is set to 0V. 

 

Then,  the  voltage  of  DC  power 

①

  is  gradually  increased  from  0V  to  predetermined  voltage  (400V). 

Monitor the VDS voltage with oscilloscope and confirm that the V

DS

 voltage rises to the set value. 

 

Input a double pulse with the pulse generator again and check the V

GS

, V

DS

 and IL waveform. 

       Observation of waveform will be easier if the trigger is applied at the rising / falling edge of V

GS

 or V

DS

 as               

       shown on Figure 13 above. 

 

If different inductor value is used other than the suggested, please set the pulse width until the desired IL 
value is achieved.

 

IL 

#1 

2.5A 

2.2µs 

5A 

4.6µs 

7.5A 

6.8µs 

10A 

9.1µs 

12.5A 

11.1µs 

15A 

13.1µs 

 

Figure 11: Usage of coil wire 

            

 

Figure 12: SMA to Probe

 

Содержание PGA26E07BA-SWEVB008

Страница 1: ...s Co Ltd 1 Kotari yakemachi Nagaokakyo Kyoto 617 8520 Japan http www semicon panasonic co jp en The products and product specifications described in the document are subject to change without notice for modification and or improvement At the final stage of your design purchasing or use of the products therefore ask for the most up to date Product Standards in advance to make sure that the latest s...

Страница 2: ...ptional parts 7 Bill of Materials 8 PCB Layout 10 Test circuits 11 Slew rate test circuit 11 Switching loss test circuit 12 Dead time circuit 12 Efficiency test circuit 13 Equipment 14 Measurement Procedures 15 Low Side dV dT test 18 High Side dV dT test 20 Low Side Switching Loss test 22 Efficiency test 24 Thermal Profile 25 Thermal Cooling 26 Important Notice 27 ...

Страница 3: ...cont 26A RDS on max 70mΩ Normally Off Device X GaN Gate Driver Supports high switching frequency 4MHz Achieved safe operation by negative voltage source and active miller clamp Facilitate gate drive design with high precision gate current source Source2 Source1 Source Drain Gate PGA26E07BA AN34092B Propagation Delay 30ns D D D D G S1 S2 S2 S2 ...

Страница 4: ... and RBS provides the bootstrap bias IC5 is Silicon Lab 2 input half bridge isolator general purpose driver Si8275GB Inputs for the half bridge isolator driver are IN_L IN_H and EN There is an LED mounted on the board to indicate EN input is high Typical Voltage for EN pin is 3 3V 5 5V SWEVB008 can also be modified to use single input PWM isolator general purpose driver e g Si8274GB The evaluation...

Страница 5: ...the gate driver IC and the design of its peripheral components are described in the OPERATION section of the datasheet Table 1 Recommended operating conditions Parameter Condition Input voltage DC Power 100V 400V Maximum Rated Power 800W Driver IC power supply voltage DC Power 12V Driver IC power supply for input stage and External clock voltage DC Power 3 3 5 5V External clock pulse generator inp...

Страница 6: ...PGA26E07BA SWEVB008 Ver 1 2 6 Schematic Diagram Refer to Figure 2 and 3 below for the circuit schematic of the evaluation board Figure 2 SWEVB008 Schematic Not populated ...

Страница 7: ...PGA26E07BA SWEVB008 Ver 1 2 7 Schematic Diagram of optional parts Figure 3 Schematic for optional isolated DCDC power supply and Optoisolator ...

Страница 8: ...uF 1000V GRM55DR72J104KW90L Murata SMD5750 C4 4 7uF 10V GRM21BR71A475KA73K Murata SMD2012 C5 0 1uF 50V GRM155R61H104KE14D Murata SMD1608 CA1 CB1 2 2uF 25V GRM31MR71E225KA93L Murata SMD3216 CA2 CB2 2 2uF 25V GRM31MR71E225KA93L Murata SMD2012 CA3 CB3 2 2nF 50V GRM2165C1H222JA01D Murata SMD2012 CA4 CB4 0 22uF 25V GRM155R61E224KE01D Murata SMD1608 CA5 CB5 0 47uF 25V GRM188R71E474KA12D Murata SMD1608 C...

Страница 9: ...r SMA2 19 46 2 TGG Multicomp SMD Isolated DCDC IC6 IC7 12Vin 12Vout MEJ2S1212SC R12P212S Murata SIP 7 Isolator IC5 2 Input Half bridge iso driver Si8275GB SiLab SOIC 16 GaN Transistor QA QB 600V 70 mΩ PGA26E07BA Panasonic SMD 8mm x 8mm Gate Driver IC1 IC2 gate driver AN34092B Panasonic QFN16 Table 3 Additional Parts use if Si8274 Isolator is used single input version of SWEVB008 Parts Symbol Speci...

Страница 10: ...PGA26E07BA SWEVB008 Ver 1 2 10 PCB Layout PCB Specifications Double sided Size 82mm 122mm Copper thickness 70um Board thickness 1 6mm Figure 4 Top and Bottom PCB Layout ...

Страница 11: ...y dead time circuit to drive isolator SI8275GB must not be overlapping This is to prevent both QA and QB turn on at the same time and the shoot through current could damage the circuit Figure 6 High Side slew rate Test circuit When the inductor L1 is connected between LX and VS buck configuration is formed also refer as high side test Please note that the output connection of the dead time circuit...

Страница 12: ...oss Test procedure is explained further in page 17 Dead time circuit Dead time circuit is required to ensure both GaN transistor QA and QB do not turn ON at the same time Figure 8 shows a simple example of dead time adjustment circuit The phasing of inverting and non inverting outputs can be fine tuned by adjusting resistor R1 XOR1 and XOR4 logic gate produce compliment of the input signal XOR2 an...

Страница 13: ...le because of the fix duty of 50 The bootstrap resistor RBS is set to 0 5Ω for 100 kHz operation For higher frequency operation do consider reducing the resistance or adopting an isolated DC DC as shown in Figure 10 The bootstrap resistor is not mounted on the board Figure 9 Circuit for efficiency test with high side circuit powered by bootstrap diode circuit Figure 10 Circuit for efficiency test ...

Страница 14: ...OUTPUT DC 600V 700W Keysight N5752A 2 DC Power 2 OUTPUT DC18V 1 5A Kenwood PW18 3 3 Pulse Generator Agilent 33250A 4 Dead time circuit General purpose Basic dead time circuit 100ns 5 Power meter 3 channel power meter Yokogawa WT500 6 Electronic Load 450V 4 5kW Chroma 63804 7 Oscilloscope Tektronix DPO7104C 8 Probe TCP0030 Current Probe IL P6139B Voltage Probe VDS VGS P5205A Differential Voltage Pr...

Страница 15: ...on board for VDS monitoring refer to Figure 11 Use an SMA to Tektronics probe adaptor as shown in Figure 12 Start up Set up the Dead time generator circuit with the amplitude 0 5V and having the double pulse profile as shown below Figure 13 Double Pulse Again ensure that the pulse generated occurs only in the burst mode If the pulse is generated continuously the transistor will be damaged by high ...

Страница 16: ...Switching Characteristics The range used is 10 90 IL condition is set at 2 5A 5A 7 5A 10A 12 5A 15A with 16 times averaging Therefore the dv dt at turn on 320V T on and the dv dt at turn off 320V T off VDS dV dT measurement during Low side device QA testing Figure 14 Measurement points for Low side device VDS dV dT measurement during High side device QB testing Figure 15 Measurement points for Hig...

Страница 17: ... time generator circuit with the amplitude 0 5V and having the double pulse profile as shown in the Figure 13 Again ensure that the pulse generated occurs only in the burst mode If the pulse is generated continuously the transistor will be damaged by high current flows Set the DC power to 5V gradually Set the DC power to 12V gradually Check VGS waveform when a double pulse is inputted from pulse g...

Страница 18: ...e 18 shows the evaluation test circuit Please refer to pages 15 16 for evaluation procedures Figure 17 Connection for Low Side GaN testing Figure 18 Evaluation Schematic for Low side GaN test AUXH AUXH VPN AUXL AUXL VDD INH GND EN GND IN_L VS LX 320uH Inductor Dead Time Circuit N5752A DC POWER PW18 3 DC power 5V 12V SMA to probe Adapter 33250A ...

Страница 19: ...64 8 V ns Turn OFF dV dt 10 2 V ns dV dt 67 5 V ns VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s Important Note The data presented is meant to demonstrate the high switching capability of Panasonic X GaN Th...

Страница 20: ...aN test High Side dV dT test Figure 23 shows all the necessary connections for High Side GaN device QB dV dT testing Figure 24 shows the evaluation test circuit Please refer to pages 15 16 for evaluation procedures Figure 24 Evaluation schematic for High side GaN test ...

Страница 21: ...div VDS 100V div Time scale 20ns div 5GS s VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s VGS 4V div IL 5A div VDS 100V div Time scale 20ns div 5GS s Important Note The data presented is meant to demonstrate the high switching capability of Panasonic X GaN The dV dT data is for reference use only and measured data maybe diffe...

Страница 22: ...essary connections for Low Side GaN device QA Switching Loss testing Figure 29 shows the evaluation test circuit Please refer to page 17 for details and evaluation procedures Figure 29 Connection for Low side switching loss test Figure 30 Test Circuit for Low side GaN switching lost test ...

Страница 23: ...iv IDS 5A div Time scale 20ns div 5GS s Time scale 20ns div 5GS s Time scale 20ns div 5GS s Power Loss uJ IL 5A div VDS 100V div IDS 5A div Power Loss uJ IL 5A div VDS 100V div IDS 5A div Power Loss uJ IL 5A div VDS 100V div IDS 5A div Important Note The data presented is meant to demonstrate the low switching loss feature of Panasonic X GaN The loss data is for reference use only and measured dat...

Страница 24: ...itions VAUXH VAUXL 12V RA1 RB1 15Ω RA2 RB2 0Ω RA3 RB3 1Ω CA3 CB3 2 2nF Test Circuit See page 13 Figure 9 High Side bias using bootstrap diode Figure 10 High Side bias using Isolated DCDC Frequency 50kHz 100kHz 200kHz VIN 200V 200V 200V Inductor 320uH 200uH 100uH Duty 50 50 50 Cooling Method Natural convection Ta 25 C Figure 35 Evaluation schematic for Boost DCDC Efficiency Evaluation Figure 36 Boo...

Страница 25: ...ured during DCDC Synchronous boost test with the following test conditions VAUXH VAUXL 12V Vin 200V Vout 390V 800W Frequency 100kHz Duty 50 Dead Time 100ns Cooling Method Natural convection Ta 25 C Figure 37 Thermal Profile of SWEVB008 in DCDC boost at 800W output power QA QB ...

Страница 26: ... Technologies T flex 600 Series Flammability Rating UL 94V0 Material Silicon with Boron Nitride filler Thermal conductivity 3 0 W mK Breakdown voltage 5 000 Vac Operating temperature 40 160 C Heat Sink Standard Quarter Brick Wakefield 537 45AB Figure 38 Mounted Heatsink information and picture ...

Страница 27: ...fringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this document Caution The evaluation board carries hazardous high voltage Do not touch when power is applied Otherwise it may cause severe injury disability or death Electric charge may be accumulated in the capacitors To prevent electrical shock please ensure all ...

Страница 28: ...PGA26E07BA SWEVB008 Ver 1 2 28 ...

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