Panasonic KMS1409096CE, Руководство по обслуживанию

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99
KX-NS500AG
15.1.2. IC401
Pin No Pin Name I/O Function
1 NIRQ_O[1] O IRQ outout
2 HW4M_I I High Way clock input
3 HW8K_I I frame sync input
4 HWDI_I I DOWN High Way
5 VCC - VCC
6 GND - GND
7 NCS_I I CPU bus chip select
8 NIRQ_EX_I[0] I IRQ input from CO_PLD
9 RST_CO_O O reset output(reserved)
10 LA_I[6] I CPU bus address
11 VCC - VCC
12 LA_I[5] I CPU bus address
13 LA_I[4] I CPU bus address
14 LA_I[3] I CPU bus address
15 LA_I[2] I CPU bus address
16 LA_I[1] I CPU bus address
17 LA_I[0] I CPU bus address
18 LD_IO[7] I/O CPU bus data
19 LD_IO[6] I/O CPU bus data
20 LD_IO[5] I/O CPU bus data
21 LD_IO[4] I/O CPU bus data
22 GND - GND
23 VCC - VCC
24 LD_IO[3] I/O CPU bus data
25 LD_IO[2] I/O CPU bus data
26 VCC - VCC
27 LD_IO[1] I/O CPU bus data
28 LD_IO[0] I/O CPU bus data
29 NIRQ_EX_I[3] I IRQ from CO OPTIN#0
30 NIRQ_EX_I[4] I IRQ from CO OPTIN#1
31 RST_EX_O[2] O CO OPTION#0 reset
32 RST_EX_O[3] O CO OPTION#1 reset
33 GND - GND
34 CNT_DLC_O[0] O DPT#0 power control
35 CNT_DLC_O[1] O DPT#0 power control
36 CNT_DLC_O[2] O DPT#1 power control
37 CNT_DLC_O[3] O DPT#1 power control
38 NC - no connection
39 CNT_RSYNC_O O ring sync output
40 NRST_SLIC O SLIC reset
41 SCLK[0] O SLIC control bus clock
42 S_CS[0] O SLIC control bus chip select
43 NIRQ_SL_I[0] I IRQ from SLIC#0
44 GND - GND
45 nHALT_O O LPR halt signal
46 VCC - VCC
47 S_CS[1] O SLIC control bus chip select
48 NIRQ_SL_I[1] I IRQ from SLIC#1
49 S_CS[2] O SLIC control bus chip select
IC401
E X T_PLD
2
9
nINT_CO0
30
nINT_CO1
31
nR
S
T_CO_OP0
3
2
nR
S
T_CO_OP1
33
GND3
34
POW
A
[0]
35
POW
A
[1]
3
6
POWB[0]
3
7
POWB[1]
38
PB10C/PCLKT
2
_1
39
RING_
SY
NC
40
nR
S
T_E
X
T
41
S
LIC_CLK0
4
2
S
LIC_C
S
0
43
S
LIC_INT0
44
GND4
45
nH
A
LT
4
6
V
CC
4
7
S
LIC_C
S
1
54
S LIC_UD
55
V CC
5 6
GND5
5 7
S LIC_DD
58
CLKOUT
59
FHOUT
6 0
D A T A OUT
6 1
NC 2
62
S LIC_CLK1
6 3
S LIC_C S 4
6 4
S LIC_INT4
6 5
S LIC_C S 5
66
S LIC_INT5
67
S LIC_C S6
6 8
S LIC_INT 6
6 9
S LIC_C S7
7 0
S LIC_INT 7
7 1
nINT_E X T0
72
GND 6
7
9
GND
7
80
V
CC
81
PROGR
A
MN
8
2
J
T
A
GENB
83
C
A
RD_ID0
84
C
A
RD_ID1
85
C
A
RD_ID
2
8
6
C
A
RD_ID3
8
7
F
A
N_
A
L
A
RM
88
nW
A
IT_IN
89
NC3
90
TM
S
91
TCK
9
2
GND8
93
V
CC
94
TDI
95
TDO
9
6
nRE
A
D
9
7
nWRITE
4 D
A T A IN
5
V CC
6
GND1
7
nC S I
8 nINT_B
AS ECO
9 nR
S T_CO
10
A6
11
V CC
1 2 A
5
13
A 4
14
A 3
15
A2
1 6 A
1
1 7 A
0
18 D
7
19 D
6
2 0 D5
2 1 D4
22
GND 2
26
V
CC
27
D1
2
8
D0
48
S
LIC_INT1
49
S
LIC_C
S2
50
V
CC
51
S LIC_INT 2
5 2
S LIC_C S 3
53
S LIC_INT3
7 3
V CC
7 4
nINT_E X T1
7 5
nR S T_E X T_OP0
76
nR
S
T_E
X
T_OP1
77
RL
Y
_
S
ET
7
8
RL
Y
_RE
S
ET
98
nW
A
IT
99
nPLD_INT#0
100
V
CC
1
nPLD_INT#1
2
HWCLK
3 FHIN
2 3
V CC
2 4 D3
2 5 D
2