2
AN33014UA Evaluation board (front side)
GND
VCC
SW1
Enable control switch
Upper side (high): DCDC ON
Lower side (low): DCDC OFF
JPFLAG
If you connect this jumper
switch, the FLAG pin will be
connected to VREG(4.9V) via
a 200k
Ω
-register.
RT resistor
DCDC output pin
(sense pin / force
pin)
Output setting: 5V
SYNC input terminal
(external clock input)
RSENSE
Current detect resistor
R-RADJ
CFB adjusting resistor
If JP4 is selected,
RT pin connected 130kW.
This setting is Fsw = 490kHz.
Ferrite beads
MPZ1608S300A
Snubber circuit
SS, CT capacitor
TL capacitor
VREG capacitor
BT capacitor
JP3
JP4
JP5
JP3
JP4
JP5
JP3
JP4
JP5
Select JP3:
RT=22kW
Fsw = 2MHz
Select JP5:
RT=330kW
Fsw = 200kHz
(below setting can select by JP3 or JP5)
C-VOUT1, 2
Output capacitor
Input capacitor
Coil
This is a two layer circuit board. The front side is shown below. (The back side is shown on the next page.)