LMX SERIES™ OPERATION MANUAL
SECTION 8:
Entire Contents Copyright
2018 by Pacific Power Source, Inc. (PPS) • All Rights Reserved • No reproduction without written authorization from PPS.
LMX Series Power Source Operation Manual
Page 365 of 463
8.12
Status and Events Registers
The IEEE488.2 standard defines a standardized status and events register system. Refer to
the ANSI/IEEE-488.2 1987 standard for more information. This section provides an overview
of these registers and bit positions for various status and error events.
8.12.1
Status Byte Register (STB)
The status register content is returned on a *STB? query. It contains 8 bits as shown in the
table below. The return value represents the 8 bits positions and can range from 0-255. A
*CLS command will clear the Status Byte Register (STB) and the Event Status Register (ESR).
Refer to Figure 8-2,”Status Byte Logical Model”.
BIT
NAME
DEFINITION
7
SOS
:STATus:OPERation register bit summary
6
MSS/RQS
- MASTER SUMMARY
summarizes all STATUS BYTE bits (except bit 6) for *STB?, or,
- REQUEST SERVICE
indicates this device requested service when a Serial Poll was
performed.
5
ESB
STANDARD EVENT STATUS REGISTER bit summary
4
MAV
MESSAGE AVAILABLE indicates Query response data is available
3
SQS
:STATus:QUEStionable register bit summary
2
EEQ
ERROR/EVENT QUEUE indicates an SCPI Error/Event message is available
1
BUSY
indicates UPC front panel not in V/I mode
0
FAULT
indicates Power Source FAULT
Table 8-4: Status Byte Register (STB)
Note:
Setting a SERVICE REQUEST ENABLE (SRE) bit true unmasks the STATUS bit in the
STB. Bit 6 of the SRE is not applicable as the MASTER SUMMARY bit of the STB
cannot be masked. The STB, SRE, ESR and ESE registers are 8 bits each.
