ozQRP CDV, Руководство по монтажу

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CDV Construction Manual – Issue 3 Page 6
2 T
HE
S
I
5351A
The heart of the CDV is the Si5351A-B-GT clock generator from Silicon Labs. This amazing
device includes two programmable Phase Locked Loops (PLL), a matrix switch, and three
programmable fractional dividers. The PLLs obtain a reference frequency from an external
25MHz crystal to generate an intermediate high frequency clock between 600MHz and 900MHz.
The PLL outputs are directed by the matrix switch to the respective fractional divider where the
PLL frequency is divided down to provide the desired output frequency. The PLL and fractional
dividers are controlled by a microcontroller via an I2C interface. Through a combination of
programmable PLL frequencies and fractional divider values the clock generator is capable of
outputting frequencies from a few KHz up to 200MHz with high accuracy and fine resolution.
The CDV uses two PLL and two fractional dividers to provide a fixed output and a variable
output. The third output is unused.