LTDVE8CH-20 – INSTRUCTION MANUAL
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14.2.12. Registers GEN_WDT_CNT[0:15]
Each bit field [9:0] of these sixteen registers holds the actual count for the generation of the pulse
width in the relevant pulse generator.
GEN_WDT_CNT0
: pulse width setting for generator 1
GEN_WDT_CNT1
: pulse width setting for generator 2
GEN_WDT_CNT2
: pulse width setting for generator 3
GEN_WDT_CNT3
: pulse width setting for generator 4
GEN_WDT_CNT4
: pulse width setting for generator 5
GEN_WDT_CNT5
: pulse width setting for generator 6
GEN_WDT_CNT6
: pulse width setting for generator 7
GEN_WDT_CNT7
: pulse width setting for generator 8
GEN_WDT_CNT8
: pulse width setting for generator 9
GEN_WDT_CNT9
: pulse width setting for generator 10
GEN_WDT_CNT10
: pulse width setting for generator 11
GEN_WDT_CNT11
: pulse width setting for generator 12
GEN_WDT_CNT12
: pulse width setting for generator 13
GEN_WDT_CNT13
: pulse width setting for generator 14
GEN_WDT_CNT14
: pulse width setting for generator 15
GEN_WDT_CNT15
: pulse width setting for generator 16
Allowed values are in the range from 1 (default value) to 1023 (maximum value). Avoid operation
with non-allowed values.
According to the time base selected in register
GEN_WDT_BASE
[x] and the count set in
GEN_WDT_CNT
[x], the pulse width may be calculated using the following formula:
Width[x] [µs] = value(GEN_WDT_BASE[x]) * value(GEN_WDT_CNT[x])
The pulse width may range from 1 µs to 1,023,000 µs with variable absolute resolution.
Bit fields [15:10] of these registers are unused. When writing these bits, they must be set to zero.
14.2.13. Registers OUTPUT_SEL_HI[0:15]
The output multiplexers are used to route the internal signals to the light outputs and synchronization
outputs. Each output multiplexer has an independent selector.
The selector of a specific output multiplexer is a 25 bits binary number, split on a pair of contiguous
Modbus registers named
OUTPUT_SEL_HI
[x] and
OUTPUT_SEL_LO
[x].
Registers
OUTPUT_SEL_HI
[x] hold in bit fields [8:0] the nine high order bits of the selectors, while
registers
OUTPUT_SEL_LO
[x] hold the remaining sixteen low order bits of the selectors.
OUT_SEL_HI0
: upper nine bits of output multiplexer 1 selector (light LD1)
OUT_SEL_HI1
: upper nine bits of output multiplexer 2 selector (light LD2)
OUT_SEL_HI2
: upper nine bits of output multiplexer 3 selector (light LD3)