ON Semiconductor NCV51705, Руководство пользователя

Страница: 8 / 16

EVBUM2528/D
www.onsemi.com
8
I/O Connectors
There are 7 I/O connectors described in Table 2 below.
The
m
C (or, PWM control IC) output (J3, J4), the XVDD and
XGND (J1, J2) and the XEN (J5) signals are noted as
“primary” ground referenced. There is no true “primary”
and “secondary” ground but there is 1.5 kV galvanic
isolation across the isolation boundary. It is especially
important to maintain isolation in high
− side, high − voltage,
switching applications where the “secondary” VDD (J6, J7)
floats VDD volts above the power supply input voltage:
Table 2. I/O CONNECTOR DESCRIPTIONS
Ref Des Name I/O GND Ref Type Description Value (V)
J1 XGND Input Primary Plated Hole External primary ground from PWM side 0
J2 XVDD Input Primary Plated Hole External VDD from PWM side (isolator bias) 5
(Note 1)
J3 IN+ Input Primary Plated Hole Non − inverting, PWM input 3.3<V
IN+
<5
(Note 1)
J4 IN − Input Primary Plated Hole Inverting PWM input 3.3<V
IN -
<5
(Note 1)
J5 XEN Output Primary Plated Hole XEN fault flag or sync signal from NCP51705 5
J6 VDD Input Secondary Plated Hole NCP51705 VDD <20
J7 GND Input Secondary Plated Hole NCP51705 secondary ground 0
J8 XGND Input Primary Plated Hole External primary ground from PWM side 0
1. The digital isolator, U2, requires that the amplitude of the PWM input (IN+ or IN − ) be equal to VDD (XVDD) and less than or equal to 5 V.