EVAL BOARD USER’S MANUAL
www.onsemi.com
Semiconductor Components Industries, LLC, 2020
December, 2021
−
Rev. 0
1
Publication Order Number:
EVBUM2797/D
NCD57253 Evaluation Board
User Manual
NCD57253GEVB
INTRODUCTION
The NCD57253 Evaluation driver board is designed for evaluation
of the NCD57253.
The NCD57253 is a high current two channel gate driver. It can
directly drive two independent MOFETs in any configuration.
The driver provides 5 kVrms internal galvanic isolation from input
to each output and functional isolation between the two output
channels. The device accepts 3.3 V to 20 V bias voltage and signal
levels on the input side and up to 32 V bias voltage on the output side.
The device accepts complementary inputs and offers separate pins for
Disable and Dead Time control for system design convenience.
NCD57253 is available in wide body SOIC
−
16 package.
DESCRIPTION
The board was created for the ability to verify and test the datasheet
parameters. The board can be externally connected to a power device
to verify real parameters in the system. It contains all the necessary
peripheral components for direct connection to the power devices. The
input bias is configured so the VDDA and VDDB can be powered by
using many types of integrated dc
−
dc power supplies or can be
powered directly from external power source. The PCB design is
optimized to reduce loop areas and provide clear and simple
measurement of all signals. All the parts (except optional dc
−
dc
sources) are TOP mounted which allows easy replacement and can
serve as an ideal reference design for future use.
Features
•
High Peak Output Current (+8 A/
−
8 A)
•
Configurable as a Dual Low
−
Side or Dual High
−
Side or Half
−
Bridge
Driver
•
Programmable Overlap or Dead Time control
•
Disable Pin to Turn Off Outputs for Power Sequencing
•
ANB Function to Offer Flexibility to Set up the Driver as
Half
−
bridge Driver Operating with a Single Input Signal
•
MOSFET Gate Clamping during Short Circuit
•
Short Propagation Delays with Accurate Matching
•
Tight UVLO Thresholds on all Power Supplies
•
3.3 V, 5 V, and 15 V Logic Input
•
5 kVrms Galvanic Isolation from Input to each Output and 1.5 kV
Peak Differential Voltage between Output Channels
•
1200 V Working Voltage (per VDE0884
−
11 Requirements)
•
High Common Mode Transient Immunity
•
High Electromagnetic Immunity
•
This Device is Pb
−
Free, Halogen Free/BFR Free and is RoHS
Compliant
•
Non
−
inverting Output Signals
Figure 1. Evaluation Board TOP View
•
PCB layout optimized for power supply
bypassing capacitor, gate
−
driver loop
•
Allows quick verification of most of the
data sheet parameters
Содержание NCD57253GEVB
Страница 16: ...NCD57253GEVB www onsemi com 16 Layout Diagrams Figure 15 Assembled PCB TOP View Figure 16 TOP Overlay...
Страница 17: ...NCD57253GEVB www onsemi com 17 Figure 17 Top Layer Figure 18 BOT Layer...
Страница 18: ...NCD57253GEVB www onsemi com 18 Figure 19 BOT Overlay Figure 20 Assembled PCB BOT View...