Omnivision CameraChip OV9650, Руководство по внедрению

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SCCB Interface
Version 1.1, December 7, 2004 Proprietary to OmniVision Technologies 47
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28 GbBIAS 80 RW
Gb Channel Signal Output Bias (effective only when COM6 [0] = 1)
Bit[7]: Bias adjustment sign
0:
Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range
29 Gr_COM 00 RW
Analog BLC and Regulator Control
Bit[7:6]: Reserved
Bit[5]:
Bypass Analog BLC
Bit[4]: Bypass regulator
Bit[3:0]: Reserved
2A EXHCH 00 RW
Dummy Pixel Insert MSB
Bit[7]: Reserved
Bit[6:4]: 3 MSB for dummy pixel insert in horizontal direction
Bit[3:2]: HSYNC falling edge delay 2 MSB
Bit[1:0]: HSYNC rising edge delay 2 MSB
2B EXHCL 00 RW
Dummy Pixel Insert LSB
8 LSB for dummy pixel insert in horizontal direction
2C RBIAS 80 RW
R Channel Signal Output Bias (effective only when COM6 [0] = 1)
Bit[7]: Bias adjustment sign
0:
Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range
2D ADVFL 00 RW LSB of insert dummy lines in vertical direction (1 bit equals 1 line)
2E ADVFH 00 RW MSB of insert dummy lines in vertical direction
2F YAVE 00 RW Y/G Channel Average Value
30 HSYST 08 RW HSYNC Rising Edge Delay (low 8 bits)
31 HSYEN 30 RW HSYNC Falling Edge Delay (low 8 bits)
32 HREF A4 RW
HREF Control
Bit[7:6]: HREF edge offset to data output
Bit[5:3]: HREF end 3 LSB (high 8 MSB at register
HSTOP )
Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART )
33 CHLF 00 RW Bit[7:0]: Reserved
34 ARBLM 03 RW Bit[7:0]: Reserved
35-36 RSVD XX – Reserved
37 ADC 04 RW Bit[7:0]: Reserved
38 ACOM 12 RW Bit[7:0]: Reserved
39 OFON 00 RW
Bit[7:4]: Reserved
Bit[3]:
Line buffer power down - must be set to "1" before chip
power down
Bit[2:0]: Reserved
Table 10-2. Device Control Register List (Continued)
Address
(Hex)
Register
Name
Default
(Hex) R/W Description