Octagon 6000 Series, Руководство пользователя, Страница: 126 / 233

6000 Series user’s manual Counter timer controller
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generate periodic interrupts, modes 2 and 3 will be most effective. The
programming example, 6020_CTC.CPP, demonstrates the use of modes
2 and 3.
Mode 0 – Terminal count
The terminal count mode is generally used to count external events.
Because the 6020 CTC is not accessed externally, this mode will not be
discussed.
Mode 1 – Hardware retriggerable one shot
To make this mode useful, load a count into either counter 0 or counter
1, or both, and then start the count by enabling the GATE. Once the
count has been reached, an interrupt will be generated from the associ-
ated counter. This mode requires control of the GATE and, therefore,
cannot be used for the counter 2 pre-scaler.
After the control word is written, OUT goes HIGH. A count value N is
written to the counter and the one shot is now armed. Any positive
transition of the GATE signal is latched and the next positive transition
of the CLOCK signal enables the one shot. The OUT signal will go
LOW on the next negative CLOCK transition and remain LOW for N
negative transitions of the CLOCK signal. When the COUNT value N
reaches a value 0, OUT will return HIGH. The ONE SHOT is
retriggerable and any positive transition on the GATE input will reload
the ONE SHOT time, which keeps OUT low for another N intervals of
CLOCK transitions.
Mode 2 – Rate generator
The rate generator mode generates an output pulse at a periodic rate.
This mode is often used for counter 2, which is the pre-scalar for
counters 0 and 1. Since the GATE of counter 2 is always enabled,
counter 2 operates in this mode. Once the count has been reached, an
output will be generated.
The OUT signal is set HIGH after the control word is written. After the
COUNT value N is written, the counter is loaded and begins to decre-
ment on CLOCK cycles. When the COUNT value reaches 0, OUT will
go LOW for one CLOCK period and then return HIGH. The N value is
automatically reloaded into the counter and is decremented on subse-
quent CLOCK pulses.
The GATE input is HIGH, which enables the counter. If the GATE
input is LOW then counting is inhibited. If GATE goes LOW during an
OUT pulse, OUT is immediately returned to a HIGH. On the rising
edge of GATE the initial N value reloads on the next CLOCK pulse.
The value decrements on subsequent CLOCK pulses.
Note A COUNT value of “1” is illegal in Mode 2.