Octagon 6000 Series, Руководство пользователя

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6000 Series user’s manual Counter timer controller
15-5
Table 15-2 Control word setup
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Table 15-3 Control word setup and description
Setup Description
D7 - SC1 Select counter bit 1
D6 - SC0 Select counter bit 0
D5 - RW1 Read/write bit 1
D4 - RW0 Read/write bit 0
D3 - M2 Mode bit 2
D2 - M1 Mode bit 1
D1 - M0 Mode bit 0
D0 - BCD Binary coded decimal enable bit
Select counter bits
Bit SC0 and bit SC1 select the correct counter for the control word.
When SC0 and SC1 select a specific counter, the remaining bits of the
control word apply to that counter.
Table 15-4 Select counter bits: SC0 and SC1
SC1 SC0 Description
0 0 Select counter 0
0 1 Select counter 1
1 0 Select counter 2
1 1 Read back command
Note For additional information on the read back command, refer to the Intel
peripheral 82C54 data sheet or the NEC 71054 data sheet.
Read/write bits
During a control word write, bit RW1 and RW0 are used to determine
the format for the data that is either read from or written to the
counters. The initial count must follow the count format specified by the
RW bits. Least significant byte only, most significant byte only, or least
significant byte and then most significant byte are the formats that can
be specified.