NY6 User Manual
Ver 1.3 2019/03/28
34
3.3 ROD
When reading data from data ROM by table read instructions, these two registers will be used to store the
higher bits of the obtained ROM data. After executing the RDN and RDNI instructions, bits [9:4] of the
obtained 10-bit ROM data will be placed in ROD2[1:0] and ROD1[3:0] and bits [3:0] of ROM data will be
placed in ACC.
3.4 INTx / INTFx ($0 ~ $03)
The INTx represents INT0 and INT1 register and controls the interrupt entrance reacts to base timer(BT),
timer counter (TM), PH counter (PHC), SPI and comparator application. The program will get into the
interrupt subroutine according to the occurrence of those interrupt sources. Users have to enable the
corresponding interrupt source first and react as the event happens.
The INTFx represents INTF0 and INTF1 register and output high if the related interrupt is issued. Those
interrupt flags can be clear by writing 0 to its bit, it won’t be reset automatically. The INTF0 register is only
reacted with four kinds of interval of base timer, 0.256ms, 0.512ms, 1.024ms, and 16.384ms.The INTF1
register is for four kinds of interrupt source, Timer counter(TM) flag issued as counter overflow, PHC flag
issued as PH counter overflow and only set for channel-1, SPI flag issued as SPI shift process is done, and
comparator flag issued as the level of VIP is higher than VIN and VIN is higher in the beginning.
Besides, those flags will keep to be launched while their events occur even if the corresponding interrupt is
disabled. The INT0/INT1 registers are to permit those events for interrupt entrance, but their flags are still
valid.
3.5 BTF ($04)
The reading source and the writing destination of the SFR[0x04] (BTF register) are different. Reading the 4-
bit data of BTF acquires the value of the BT counter. The NY6 series provides 4 different base timer
intervals for polling: 0.256ms, 0.512ms, 1.024ms and 16.384ms. The value of time means the period, so
polling and finding data toggle means half time of the interval.
Writing BTF is to apply for memory lock
function only for 0x3E and 0x3F address in SRAM. Writing 0x5 is to unlock for current address and lock
after this cycle accomplished, users has to write 0x5 again to unlock for next address, 0x3E or 0x3F.
INT[0]
INT[1]
INT[2]
INT[3]
0.512ms
1.024ms
0.256ms
16.384ms
INT Timing Figure
