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NXP Semiconductors
UM11666
SC18IS606-EVB evaluation board
JP2 – I
2
C Header
Function
1
-Reset
2
-INT (interrupt)
3
SCL
4
Ground
5
VCC
6
SDA
Table 3. JP2 - I
2
C
JP3 – SC18IS606 I
2
C
target address
1 -2
3 -4
5 -6
0x50
ON
ON
ON
0x51
OFF
ON
ON
0x52
ON
OFF
ON
0x53
OFF
OFF
ON
0x54
ON
ON
OFF
0x55
OFF
ON
OFF
0x56
ON
OFF
OFF
0x57
OFF
OFF
OFF
Table 4. JP3 – SC18IS606 I
2
C target address
4.3 Schematic, board layout and bill of materials
The schematic, board layout and bill of materials for the SC18IS606-EVB evaluation
http://www.nxp.com/SC18IS606-EVB
.
4.4 Sample control sequences from I
2
C controller
4.4.1 GPIO as input
Write 0x50 0xF6 0x07 // program chip select pins as GPIO
Write 0x50 0xF7 0xAA // configure GPIOs as inputs
Write 0x50 0xF5 // read inputs into buffer
Read 0x51 // read input pins state from buffer
4.4.2 GPIO as output
Write 0x50 0xF6 0x01 // program SS0 as GPIO
Write 0x50 0xF7 0x55 // GPIO pins as push-pull
Write 0x50 0xF4 0x00 // Set SS0 to ‘0’
Write 0x50 0xF4 0x01 // Set SS0 to ‘1’
UM11666
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© NXP B.V. 2021. All rights reserved.
User manual
Rev. 1.0 — 28 September 2021
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