NXP Semiconductors
UM11666
SC18IS606-EVB evaluation board
1 Introduction
SC18IS606 is designed to operate as an I
2
C target and an SPI master. SC18IS606
controls all the SPI bus specific sequences, protocol, and timing. SC18IS606 has its own
internal oscillator, and it supports three SPI chip select outputs that may be configured as
GPIO when not used as SPI chip selects.
This document is intended to help the users to quickly setup, configure and operate the
SC18IS606-EVB evaluation board in the users’ hardware platform.
2 Finding kit resources and information on the NXP web site
NXP Semiconductors provides online resources for this evaluation board and its
supported device(s) on
The information page for SC18IS606-EVB evaluation board is at
. The information page provides overview information, documentation,
parametrics, ordering information and a
Getting Started
tab. The
Getting Started
tab
provides quick-reference information applicable to using the SC18IS606-EVB evaluation
board, including the downloadable assets referenced in this document.
2.1 Collaborate in the NXP community
The NXP community is for sharing ideas and tips, ask and answer technical questions,
and receive input on just about any embedded design topic.
The NXP community is at
3 Getting ready
Working with the SC18IS606-EVB evaluation board requires the kit contents.
3.1 Kit contents
•
Assembled and tested evaluation board in an anti-static bag
•
Quick Start Guide
4 Getting to know the hardware
The SC18IS606-EVB evaluation board is designed to be connected to an external I
2
C
controller via a 6-pin male (JP2) header. The SC18IS606-EVB evaluation board has an
on-board SPI slave serial EEPROM, which can be directly accessed by the external I
2
C
controller via SC18IS606. The external I
2
C controller can write, read, and program the
serial EEPROM without requiring an SPI slave to be connected to the board.
The 3V3 power for the SC18IS606-EVB evaluation board should be supplied via this I
2
C
interface header as well.
The SC18IS606-EVB evaluation board also has an SPI interface header (JP1) to allow
other SPI slave devices to be connected to the evaluation board. These SPI slave
devices can be accessed directly by the I
2
C controller via the SC18IS606 I
2
C to SPI
bridge.
UM11666
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
User manual
Rev. 1.0 — 28 September 2021
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