Chapter 25 FlexPWM
MPC5602P Microcontroller Reference Manual, Rev. 4
660
Freescale Semiconductor
25.6.3.4
Control 1 Register (CTRL1)
13
RELOAD_SEL
Reload Source Select
This read/write bit determines the source of the RELOAD signal for this submodule. When this bit
is set, the LDOK bit in submodule 0 should be used since the local LDOK bit will be ignored.
0 The local RELOAD signal is used to reload registers.
1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should
not be used in submodule 0 as it will force the RELOAD signal to logic 0.
14:15
CLK_SEL
Clock Source Select
These read/write bits determine the source of the clock signal for this submodule.
00 The IPBus clock is used as the clock for the local prescaler and counter.
01 EXT_CLK is used as the clock for the local prescaler and counter.
10 Submodule 0’s clock (AUX_CLK) is used as the source clock for the local prescaler and counter.
This setting should not be used in submodule 0 as it will force the clock to logic 0.
11 Reserved.
Address: Base + 0x0006 (Submodule 0)
Base + 0x0056 (Submodule 1)
Base + 0x00A6 (Submodule 2)
Base + 0x00F6 (Submodule 3)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
LDFQ
HALF FULL
DT
0
PRSC
0
0
0
DBL
EN
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-6. Control 1 Register (CTRL1)
Table 25-4. CTRL1 field descriptions
Field
Description
0:3
LDFQ
Load Frequency
These buffered read/write bits select the PWM load frequency according to
Reset
clears the LDFQ bits, selecting loading every PWM opportunity. A PWM opportunity is determined
by the HALF and FULL bits.
The LDFQ
x
bits take effect when the current load cycle is complete regardless of the state of the
LDOK bit. Reading the LDFQx bits reads the buffered values and not necessarily the values
currently in effect. See
.
4
HALF
Half Cycle Reload
This read/write bit enables half-cycle reloads. A half cycle is defined by when the submodule
counter matches the VAL0 register and does not have to be half way through the PWM cycle.
0 Half-cycle reloads disabled.
1 Half-cycle reloads enabled.
Table 25-3. CTRL2 field descriptions (continued)
Field
Description
Содержание SAFE ASSURE Qorivva MPC5601P
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