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NXP Semiconductors S32G-VNP-GLDBOX, Справочное руководство

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NXP Semiconductors S32G-VNP-GLDBOX Скачать руководство пользователя страница 21

 

21 

 

3.2    Boot 

The BootROM in S32G2 is responsible for booting the customer applications and the HSE_H FW. It 
supports Serial Boot, Boot from RCON and Boot from fuses. Combined values of Boot mode pins, 
FUSE_SEL fuses and Lifecycles control the boot mode 

1

. Boot from fuses requires the FUSE_SEL fuses to 

be blown before S32G2 booting. By default, the FUSE_SEL fuses of the S32G2 are not blown 

2

 and 

therefore the S32G-VNP-GLDBOX shipped from the factory only supports two boot modes: serial boot mode 
and boot from RCON. The figure below shows the related circuit of the boot mode pin0 and pin1. 
 

S32G274

INV

INV_RESET_B

74CBTLV3253DS

GND

P3.3V

INV

INV_RESET_B

74CBTLV3253DS

GND

P3.3V

BOOT MODE0(PA_02)

BOOT MODE1(PA_03)

INPUT1

INPUT2

INPUT3

INPUT4

OUPUT

INPUT1

INPUT2

INPUT3

INPUT4

OUPUT

SW10

ON

OFF

OFF

ON

1

2

OFF

OFF

ON

2

1

ON

SW9

S0

S1

S1

S0

RESET_B

RESET_B

RESET_B

RESET_B

 

Figure 4. Boot mode pins

 

 
The values of boot mode pin0 and pin1 are controlled by SW9 and SW10. The table below shows boot 
mode pin values and the corresponding settings of SW9 and SW10. 
 

 
 

 
 

 

1

 Please refer to the Chapter 30 of the S32G2 Reference Manual for more detail about the boot mode. 

2

 For the method of blowing FUSE_SEL fuses, please contact your local field applications engineer (FAE) or sales 

representative. 

Содержание S32G-VNP-GLDBOX

Страница 1: ...1 S32G VNP GLDBOX Reference Manual Version 0 4 ...

Страница 2: ... 12 2 6 Buttons 13 2 7 Power switch 13 2 8 DIP Switches 14 2 9 Jumpers 17 2 10 LEDs 18 3 Functional Descriptions 19 3 1 Power supply 19 3 2 Boot 21 3 3 Reset 23 3 4 Clocks 24 3 5 JTAG Connections 25 3 6 Aurora Trace 25 3 7 External Memory and Storage 25 3 7 1 LPDDR4 25 3 7 2 NOR flash 26 3 7 3 SD eMMC 26 3 8 SerDes interfaces 27 3 9 Ethernet 28 3 9 1 Automotive Ethernet switch 29 3 9 2 Ethernet PH...

Страница 3: ...3 3 11 LIN and UART 35 3 12 FlexRay 36 3 13 DSPI 36 3 14 I2C 37 3 15 USB 38 4 Cables Description 39 5 Revision History 43 ...

Страница 4: ...umpers on the S32G VNP GLDBOX 17 Table 12 LEDs on the S32G VNP GLDBOX 18 Table 13 Values of the boot mode pins 22 Table 14 The memory map of the DDR and NOR Flash 25 Table 15 SerDes_0 work modes and corresponding settings 27 Table 16 SerDes_1 work modes and corresponding settings 28 Table 17 SJA1110 Ethernet port connections 30 Table 18 Ethernet PHY description 30 Table 19 SMI interfaces 31 Table ...

Страница 5: ...EV D20 Figure 4 Boot mode pins 21 Figure 5 RCON pins 22 Figure 6 Reset tree of S32G VNP GLDBOX 23 Figure 7 Clock tree of S32G VNP GLDBOX REVD 24 Figure 8 The connection of LPDDR4 SDRAM 25 Figure 9 Connection between S32G274A and the NOR flash chip 26 Figure 10 Connections between S32G274A and SD eMMC 27 Figure 11 Ethernet connection diagram of S32G VNP GLDBOX 29 ...

Страница 6: ...em partners to accelerate development for a shorter time to market This document describes the hardware features of the board specifications block diagram connectors and interfaces 1 1 Acronyms and abbreviations The table below lists commonly used acronyms and abbreviations Table 1 Acronyms and abbreviations Acronym abbreviation Description CAN Controller Area Network CAN FD CAN with Flexible Data...

Страница 7: ...elated documentation The table below lists the documents that can be referred to for more information on the S32G VNP GLDBOX Some of the documents listed below may be available only under a non disclosure agreement NDA To request access to these documents please contact your local field applications engineer FAE or sales representative Table 2 Related documentation Document Description S32G2 Produ...

Страница 8: ... GLDBOX Table 3 S32G VNP GLDBOX board versions PCBA version Schematic Brief revision information Board version REV C SCH 47800 REVC The first orderable version of the S32G VNP GLDBOX Board version REV D SCH 47800 REVD 1 Added core current measurement circuit The core current information can be obtained by I2C4 2 Added temperature measurement circuit The board temperature information can be obtaine...

Страница 9: ...ffload with Low Latency Communications Engine LLCE Gigabit Ethernet Packet Forwarding Engine PFE 8MB Embedded System RAM with ECC 32KB Standby RAM with ECC Memory LPDDR4 1 x LPDDR4 4GB with inline ECC and self refresh NOR flash 1 x NOR Flash 64MB eMMC 1 x eMMC 32GB SD card 1 x Slot for SD card Connectivity Ethernet 1 x 100BASE TX 6 x 100BASE T1 5 x 1000BASE T USB 1 x USB 2 0 port as host device mo...

Страница 10: ... UART USB FT232 Boot mode select circuit Parallel RCON select circuit PMIC VR5510 USB 2 0 Phy USB83340 CAN Phy TJA1043 6 pcs UART USB FT232 CAN Phy TJA1463 6 pcs CAN Phy TJA1153 4 pcs CAN Phy TJA1043 2 pcs PMIC FS5600 PMIC PF5300 PMIC PF5020 PMIC PF5020 Load Switch GMAC0 PFE_MAC2 SerDes1 SerDes0 100Base T1 Phy x6 100Base Tx Phy 100Base T1 x6 ch 100Base Tx Port 2 Port 3 RGMII RGMII PCIe X2 PCIe X2 ...

Страница 11: ...the S32G VNP GLDBOX PCB Table 5 S32G VNP GLDBOX PCB specifications Items Specifications Ambient temperature 35 C Lab environment PCB dimensions 180mm x 140mm 2 4 Top view The figure below shows the top view of the S32G VNP GLDBOX Figure 2 The top view of S32G VNP GLDBOX ...

Страница 12: ... 2 x 10 connector SJA1110 JTAG header Connects to the debugger J47 M 2 M key slot PCIe x2 M 2 slot with key M and supports PCIe x2 Gen3 Gen2 Gen1 and PCIe x1 Gen3 Gen2 Gen1 Connects to PCIe x2 module size 2242 key M key B M key It is recommended to connect 2242 B M key NVME SSD such as TOSHIBA RC100 240G which has been already tested on S32G VNP GLDBOX If J47 is used J56 is not available J48 2 x 1...

Страница 13: ...ns The table below describes the buttons of the S32G VNP GLDBOX Table 7 The buttons of the S32G VNP GLDBOX Part Name Description SW1 POR_B Press SW1 to reset the system S32G274A will perform a power on reset SW2 RESET_B Press SW2 to reset the system S32G274A will perform functional reset SW16 NMI Press SW16 to assert non maskable interrupt 2 7 Power switch The table below describes the power switc...

Страница 14: ...word BOOT_CFG1 0 1 OFF S32G274A Fuse word BOOT_CFG1 0 0 SW4 2 OFF ON S32G274A Fuse word BOOT_CFG1 1 1 OFF S32G274A Fuse word BOOT_CFG1 1 0 SW4 3 OFF ON S32G274A Fuse word BOOT_CFG1 2 1 OFF S32G274A Fuse word BOOT_CFG1 2 0 SW4 4 OFF ON S32G274A Fuse word BOOT_CFG1 3 1 OFF S32G274A Fuse word BOOT_CFG1 3 0 SW4 5 OFF ON S32G274A Fuse word BOOT_CFG1 4 1 OFF S32G274A Fuse word BOOT_CFG1 4 0 SW4 6 OFF ON...

Страница 15: ...ord BOOT_CFG1 15 1 OFF S32G274A Fuse word BOOT_CFG1 15 0 SW6 1 OFF ON S32G274A Fuse word BOOT_CFG1 16 1 OFF S32G274A Fuse word BOOT_CFG1 16 0 SW6 2 OFF ON S32G274A Fuse word BOOT_CFG1 17 1 OFF S32G274A Fuse word BOOT_CFG1 17 0 SW6 3 OFF ON S32G274A Fuse word BOOT_CFG1 18 1 OFF S32G274A Fuse word BOOT_CFG1 18 0 SW6 4 OFF ON S32G274A Fuse word BOOT_CFG1 19 1 OFF S32G274A Fuse word BOOT_CFG1 19 0 SW6...

Страница 16: ...DHC interface to eMMC SW8 1 ON Refer to 3 8 SerDes interface for more detail SW17 1 ON Refer to 3 8 SerDes interface for more detail SW12 1 ON 1 ON 2 ON SJA1110 performs SDL boot 1 ON 2 OFF SJA1110 performs NVM boot using SPI Flash 1 OFF 2 OFF Reserved 1 OFF 2 ON Reserved SW12 2 OFF SW11 1 OFF ON Connects GPIO6 GPIO7 GPIO95 to U128 RGB LED OFF Connects GPIO6 GPIO7 GPIO95 to J5 connector SW9 1 OFF ...

Страница 17: ... on the S32G VNP GLDBOX Part Type Default setting Description J184 1 x 2 connector 1 2 Shorted 1 2 Open VR5510 enters normal mode after power on Watchdog will be enabled 1 2 Shorted VR5510 enters debug mode after power on Watchdog will be disabled J180 2 x 2 connector 1 2 Shorted 3 4 Shorted Reserved J181 2 x 2 connector 1 2 Open 3 4 Open Reserved J185 1 1 x 2 connector 1 2 Open 1 2 Open Disconnec...

Страница 18: ...7 Red Green Lights up in red UART1 output is in progress Lights up in green UART1 input is in progress D8 Red Green Lights up in red UART0 output is in progress Lights up in green UART0 input is in progress D36 Green Lights up when the SSD status is available D2 Red top Lights up when the board is resetting Green bottom Lights up when the board is power on U128 Green Lights up when GPIO95 keeps LO...

Страница 19: ... DC power adapter and the onboard PMIC The specifications of the 12V AC DC power adapter are listed below Input 110 240V AC 50 60 Hz Output 12 V 6 67A AC DC 80W MAX The figure below shows the power supply block diagram of the S32G VNP GLDBOX REV D For the power supply block diagram of S32G VNP GLDBOX please refer to SCH 47800_C pdf ...

Страница 20: ...DD_VREF VDD_ADC VDD_IO_PCIE0 1 VDD_IO_AUR VDD_IO_CLKOUT VDD_HV_PLL_AUR VDD_HV_PLL_DDR0 VDD_HV_PLL VDD_DDR0 VDD_TMU VDD_FXOSC VDD_FIRC U43 S32G VDD_EFUSE U25 MAX4886 VDD U31 MAX4886 VDD U44 MAX4886 VDD U38 MAX4886 VDD U13 MCP6022 VDD U11 MCP6022 VDD U12 MCP6022 VDD J48 S32G JTAG U8 USB83340 VDDIO U3 FT232 VCCIO U2 FT232 VCCIO J57 AURORA U43 S32G VDD_IO_USB VDD_IO_A VDD_IO_B VDD_IO_GMAC0 1 U43 S32G ...

Страница 21: ...he related circuit of the boot mode pin0 and pin1 S32G274 INV INV_RESET_B 74CBTLV3253DS GND P3 3V INV INV_RESET_B 74CBTLV3253DS GND P3 3V BOOT MODE0 PA_02 BOOT MODE1 PA_03 INPUT1 INPUT2 INPUT3 INPUT4 OUPUT INPUT1 INPUT2 INPUT3 INPUT4 OUPUT SW10 ON OFF OFF ON 1 2 OFF OFF ON 2 1 ON SW9 S0 S1 S1 S0 RESET_B RESET_B RESET_B RESET_B Figure 4 Boot mode pins The values of boot mode pin0 and pin1 are contr...

Страница 22: ...amely the RCON 0 to RCON 31 uses up to 32 general purpose I O pins They are latched on functional reset deassertion RCON 31 0 corresponds bit by bit to values in the fuse word BOOT_CFG1 31 0 The values of these pins will be sampled only in S32G274A reset stage so they can also be used as other functions when BootROM finish the sample The figure below shows the diagram of RCON pins MAX4886ETO PA 9 ...

Страница 23: ...so be reset by S32G274A GPIO and the Ethernet PHYs can also be reset by S32G274A GPIOs or SJA1110 GPIO P3_3V_IO3P3 U94 FS5600 U96 PF5020 U108 PF5020 U41 VR5510 U43 S32G STBY_PGOOD RESET_B J48 JTAG J47 Aurora U5 P3_3V_STBY_BRD SW2 P3_3V_STBY_BRD P3_3V_STBY_BRD U33 U37 QSPI U113 U84 KSZ9031 RGMII_VDD U115 U58 KSZ9031 RGMII_VDD U8 USB83340 P1 PCIe X1 socket J47 M 2 M key slot J56 M 2 E key slot U116 ...

Страница 24: ... Multiplexer SD0_CLK SD0_CMD SD0_D0 3 DDR0_A_00 05 DDR0_A_08 13 DDR0_A_20 25 DDR0_A_28 33 DDR0_D_00 46 DDR_RESET U42 LPDDR4 MT53D1024M32D4 GMAC0_TX_EN GMAC0_TX_CLK GMAC0_TXD0 3 GMAC0_RX_CLK GMAC0_RXDV GMAC0_RXD0 3 U84 1000Base T Phy KSZ9031 Y10 25MHz PFE_MAC2_TX_EN PFE_MAC2_TX_CLK PFE_MAC2_TXD0 3 PFE_MAC2_RX_CLK PFE_MAC2_RXDV PFE_MAC2_RXD0 3 GMAC0_MDC GMAC0_MDIO PFE_MAC2_MDC PFE_MAC2_MDIO U58 1000...

Страница 25: ...d NOR Flash Memory Start End DDR M7 0x00_6000_0000 0x00_DFFF_FFFF DDR A53 0x08_0000_0000 0x08_FFFF_FFFF NOR Flash 0x00_0000_0000 0x00_1FFF_FFFF 3 7 1 LPDDR4 S32G VNP GLDBOX has a single 1024 Meg x 32 2 channels x 16 I O LPDDR4 SDRAM chip MT53D1024M32D4DT 046 AUT D for a total RAM memory of 4GB and it supports inline ECC and self refresh The DDR interfaces use power sources of 1 1VDC and 1 8VDC whi...

Страница 26: ... NOR flash QSPI S32G NOR Flash MX25UW51245GXDQ00 CS DATA7 QSPI_A_CS0 QSPI_A_DATA0 QSPI_A_DQS Level shifter QSPI_A_CK QSPI_A_DATA1 QSPI_A_DATA2 QSPI_A_DATA3 QSPI_A_DATA4 QSPI_A_DATA5 QSPI_A_DATA6 QSPI_A_DATA7 RESET_B DATA0 DATA5 DATA1 DATA2 DATA4 DATA3 DATA6 SO SIO1 SIO2 SIO4 SIO6 SIO3 SIO5 SIO7 SI SIO0 DQS 1 8V 0 QSPI_A_INT 10K SCLK 1 8V 4 7K 4 7K RESET 1 8V ECS 4 7K Figure 9 Connection between S3...

Страница 27: ...SEL SW3 Figure 10 Connections between S32G274A and SD eMMC There are two analog switches MAX4886 between the connections shown in the figure above One analog switch is used for multiplexing control signals and the other is used for multiplexing data signals When SW3 is ON SD card is selected When SW3 is OFF the eMMC card is selected 3 8 SerDes interfaces The S32G274A on the S32G VNP GLDBOX has two...

Страница 28: ... Gbps PFE_MAC1 AQR113C SGMII only usage 2 Default Lan0 SGMII 3 125 Gbps PFE_MAC0 SJA1110 P4 Lan1 S32G2 Not available NA 3 9 Ethernet The GMAC of the S32G2 enables a host application to transmit and receive data over an Ethernet network in compliance with IEEE 802 3 2015 and the PFE of S32G2 offloads the processing of Ethernet packets from the host cores and can provide higher performance and lower...

Страница 29: ...I RGMII RGMII PFE_MAC0 PFE_MAC2 RGMII Port RGMII P3A RJ45 P3B RJ45 P2A RJ45 P2B RJ45 P4 RJ45 P5 RJ45 J53 Mini50 Figure 11 Ethernet connection diagram of S32G VNP GLDBOX 3 9 1 Automotive Ethernet switch The S32G VNP GLDBOX has an automotive Ethernet switch SJA1110 which mainly comprises of a configurable Ethernet switch and a programmable M7 core Except the Ethernet ports and SMI bus port the SJA11...

Страница 30: ... 100BASE T1 Mini50 connector P8 100BASE T1 Mini50 connector P9 100BASE T1 Mini50 connector P10 100BASE T1 Mini50 connector 3 9 2 Ethernet PHYs The table below describes the Ethernet PHY on the S32G VNP GLDBOX Table 18 Ethernet PHY description Part P N Connection Signal Description U56 AR8035 SJA1110 P3 RGMII 1000BASE T U57 AR8035 SJA1110 P2 RGMII 1000BASE T U58 KSZ9031 S32G274A PFE_MAC2 RGMII 1000...

Страница 31: ...Y2 P6 0X0A 100BASE T1 PHY3 P7 0X0B 100BASE T1 PHY4 P8 0X0C 100BASE T1 PHY5 P9 0X0D 100BASE T1 PHY6 P10 0X0E SJA1110 SMI_OUT_MDC SMI_OUT_MDIO U57 AR8035 0X04 U56 AR8035 0X05 3 10 CAN The table below describes the CAN PHY connections on the S32G VNP GLDBOX Table 20 CAN PHY connections CAN PHY Connections Signal U17 TJA1043 TXD U43 S32G274A PC_12 LLCE_CAN0_TXD RXD U43 S32G274A PC_11 LLCE_CAN0_RXD EN ...

Страница 32: ...JA1043 TXD U43 S32G274A PJ_05 LLCE_CAN3_TXD RXD U43 S32G274A PJ_06 LLCE_CAN3_RXD EN U24 PCAL6524HEAZ P0_5 LLCE_CAN3_EN STB U24 PCAL6524HEAZ P0_4 LLCE_CAN3_STB U20 TJA1153 TXD U43 S32G274A PJ_11 LLCE_CAN6_TXD RXD U43 S32G274A PJ_12 LLCE_CAN6_RXD EN U24 PCAL6524HEAZ P1_1 LLCE_CAN67_EN STB U24 PCAL6524HEAZ P1_0 LLCE_CAN67_STB U69 TJA1153 TXD U43 S32G274A PJ_13 LLCE_CAN7_TXD RXD U43 S32G274A PJ_14 LLC...

Страница 33: ...TB U24 PCAL6524HEAZ P1_4 LLCE_CANAB_STB U99 TJA1463 TXD U43 S32G274A PK_11 LLCE_CAN14_TXD RXD U43 S32G274A PK_12 LLCE_CAN14_RXD EN U24 PCAL6524HEAZ P2_1 LLCE_CANEF_EN STB U24 PCAL6524HEAZ P2_0 LLCE_CANEF_STB U98 TJA1463 TXD U43 S32G274A PK_13 LLCE_CAN15_TXD RXD U43 S32G274A PK_14 LLCE_CAN15_RXD EN U24 PCAL6524HEAZ P2_1 LLCE_CANEF_EN STB U24 PCAL6524HEAZ P2_0 LLCE_CANEF_STB U19 TJA1153 TXD U43 S32G...

Страница 34: ... U24 PCAL6524HEAZ P1_3 LLCE_CAN89_EN STB U24 PCAL6524HEAZ P1_2 LLCE_CAN89_STB U68 TJA1463 TXD U43 S32G274A PK_01 LLCE_CAN9_TXD RXD U43 S32G274A PK_02 LLCE_CAN9_RXD EN U24 PCAL6524HEAZ P1_3 LLCE_CAN89_EN STB U24 PCAL6524HEAZ P1_2 LLCE_CAN89_STB U22 TJA1463 TXD U43 S32G274A PK_07 LLCE_CAN12_TXD RXD U43 S32G274A PK_08 LLCE_CAN12_RXD EN U24 PCAL6524HEAZ P1_7 LLCE_CANCD_EN STB U24 PCAL6524HEAZ P1_6 LLC...

Страница 35: ...4 TJA1043 TXD U43 S32G274A PB_03 FLEX_CAN1_TXD RXD U43 S32G274A PB_04 FLEX_CAN1_RXD EN U24 PCAL6524HEAZ P2_5 FLEX_CAN1_EN STB U24 PCAL6524HEAZ P2_4 FLEX_CAN1_STB 3 11 LIN and UART The table below describes the LIN and UART connections on the S32G VNP GLDBOX Table 21 LIN and UART connections PHY S32G274A IO Description U3 FT232RQ TXD PC_10 UART0 RXD PC_09 U3 FT232RQ TXD PA_13 UART1 RXD PB_00 U9 TJA...

Страница 36: ...table below describes the FlexRay connections on the S32G VNP GLDBOX Table 22 FlexRay connections FlexRay PHY Connection Signal U23 TJA1081 TXD U43 S32G274A PL_02 LLCE_FR_TXD_A TXEN U43 S32G274A PL_01 LLCE_FR_TXE_A RXD U43 S32G274A PL_03 LLCE_FR_RXD_A STBN U24 PCAL6524HEAZ P2_6 EIO_FR_STBN_A EN U24 PCAL6524HEAZ P2_7 EIO_FR_EN_A 3 13 DSPI The table below describes the DSPI connections on the S32G V...

Страница 37: ... Connects to SJA1110 3 14 I2C The I2C module is a functional unit that provides a two wire bidirectional serial bus Its operating speed can be up to 100 kbps in the standard mode and up to 400 kbps in the fast mode The table below describes the I2C connections on the S32G VNP GLDBOX Table 24 I2C connections S32G274A Interface Part Address Description I2C0_SCL PC_00 I2C0_SDA PB_15 U83 PCA85073A 101...

Страница 38: ...5 USB The USB PHY connects to external USB devices through J4 MICRO_AB and supports both Host mode through the OTG cable and Device mode through the USB A to Micro B cable When the USB PHY works in Host mode it is recommended that the load current of the connected USB device MUST be less than 1A The table below describes the USB connections on the S32G VNP GLDBOX Table 25 USB connections USB Phy S...

Страница 39: ...exCAN1_L LLCE_CAN0_H Yellow 8 7 White LLCE_CAN0_L LLCE_CAN1_H Yellow 10 9 White LLCE_CAN1_L LLCE_CAN2_H Yellow 12 11 White LLCE_CAN2_L LLCE_CAN3_H Yellow 14 13 White LLCE_CAN3_L LLCE_CAN4_H Yellow 16 15 White LLCE_CAN4_L LLCE_CAN5_H Yellow 18 17 White LLCE_CAN5_L LLCE_CAN6_H Yellow 20 19 White LLCE_CAN6_L LLCE_CAN7_H Yellow 22 21 White LLCE_CAN7_L LLCE_CAN8_H Yellow 24 23 White LLCE_CAN8_L LLCE_CA...

Страница 40: ...J5 Cable Signal Cable color connector connector Cable color Signal 12_VIN Red 2 1 Orange 5V_OUT 12V_OUT Orange 4 3 Orange 3V3_OUT GND Black 6 5 Black GND FLEX_LIN2 Blue 8 7 Black GND LLCE_LIN0 Blue 10 9 Blue LLCE_LIN1 LLCE_LIN2 Blue 12 11 Blue LLCE_LIN3 PB_05 GPIO 21 I2C2_SCL External IRQ2 White 14 13 White PB_06 GPIO 22 I2C2_SDA External IRQ3 PA_06 GPIO 6 DSPI1_SOUT FTM1_CH2 Yellow 16 15 Yellow P...

Страница 41: ...n 24 23 Green ADC_IN2 ADC_IN3 Green 26 25 Green ADC_IN4 The table below describes the Cable of Connector J53 Table 28 J53 Cable Connector Signal Cable color 1 2 3 100Base T1 TRX6 White 4 Yellow 5 6 7 100Base T1 TRX9 White 8 Yellow 9 10 11 100Base T1 TRX5 White 12 Yellow 13 ...

Страница 42: ...42 14 15 100Base T1 TRX7 White 16 Yellow 17 18 19 100Base T1 TRX8 White 20 Yellow 21 22 23 100Base T1 TRX10 White 24 Yellow ...

Страница 43: ... GLDBOX REVD 2 Added descriptions of J185 J186 J187 for S32G VNP GLDBOX REVD 3 Updated the overview diagram power tree reset tree and clock tree for S32G VNP GLDBOX REVD 4 Added U136 U137 to the I2C chapter for S32G VNP GLDBOX REVD 5 Ethernet PHY chapter changed AQR107 to AQR113C for S32G VNP GLDBOX REVD 6 Added PF5300 I2C address ...

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