NXP Semiconductors RDGD31603PHSEVM, Руководство пользователя

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NXP Semiconductors
UM11603
RDGD31603PHSEVM three-phase inverter reference design
Test point name Function
FSISHV FSISO connection
FSISLU FSISO connection
FSISLV FSISO connection
FSISLW FSISO connection
GHU Gate high-side U phase which is the charging pin of IGBT gate
GHV Gate high-side V phase which is the charging pin of IGBT gate
GHW Gate high-side W phase which is the charging pin of IGBT gate
GLU Gate low-side U phase which is the charging pin of IGBT gate
GLV Gate low-side V phase which is the charging pin of IGBT gate
GLW Gate low-side W phase which is the charging pin of IGBT gate
NCLU – NCHW INTA Interrupt output signal test points from each gate driver
Resolver circuit Test points for internal signals of resolver circuit (see schematic for more
information)
MCU signals Signal headers for analyzing all MCU signals (see schematic for signals)
TSENSEHU TSENSE high-side U phase connected to NTC temperature sense
TSENSEHV TSENSE high-side V phase connected to NTC temperature sense
TSENSEHW TSENSE high-side W phase connected to NTC temperature sense
TSENSELU TSENSE low-side U phase
TSENSELV TSENSE low-side V phase
TSENSELW TSENSE low-side W phase
VREFLU 5.0 V reference voltage test point low-side U phase
VREFHU 5.0 V reference voltage test point high-side U phase
VREFLV 5.0 V reference voltage test point low-side V phase
VREFHV 5.0 V reference voltage test point high-side V phase
VREFLW 5.0 V reference voltage test point low-side W phase
VREFHW 5.0 V reference voltage test point high-side W phase
VSUP VSUP/VPWR test point low voltage domain
Table 2. Test points
...continued
4.2.4 Indicators
The RDGD31603PHSEVM evaluation board contains LEDs as visual indicators on the
board.
UM11063 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 18 August 2021
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