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NXP Semiconductors

JN-RM-2079

QN9090 module development reference manual

JN-RM-2079

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2020. All rights reserved.

Reference manual

Rev. 1.0

— 17 Jan 2020

20 of 31

Fig 17. Solder paste mask for HVQFN40 40-pin QFN

Fig 18. Vias on the paddle of the HVQFN40 40-pin QFN

25 vias are applied to the paddle. These allow excess solder paste and heated air to be
vented away from the device, preventing the device from being lifted during soldering.
In addition, these vias ensure that a low impedance ground is maintained, which is vital
for optimum RF performance.

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Содержание QN9090

Страница 1: ...2079 QN9090 module development reference manual Rev 1 0 17 Jan 2020 Reference manual Document information Info Content Keywords QN9090 module Abstract Reference Manual for QN9090 modules and platform...

Страница 2: ...ormation provided in this document is subject to legal disclaimers NXP Semiconductors N V 2020 All rights reserved Reference manual Rev 1 0 17 Jan 2020 2 of 31 Contact information For more information...

Страница 3: ...x M4 processor up to 640 kB flash 152 kB SRAM and 128 kB ROM BLE Link layer processing hardware and peripherals optimized to meet the requirements of the target applications The design considerations...

Страница 4: ...yout Bill of Materials Full design databases including schematics and layout source files are available on request The following table provides a summary of the QN9090 Module Reference Design that is...

Страница 5: ...ircuit matching antenna design and RF measurement capability are essential RF circuit design layout and antenna design are specialties requiring investment in tools and experience With available hardw...

Страница 6: ...rious radiation and range will have a high likelihood of first time success The following subsections describe important considerations when implementing a wireless hardware design starting with the d...

Страница 7: ...s RF output and ground traces Die flag shape 4 2 PCB Stack Up Complexity is the main factor that will determine whether the design of an application board can be two layer four layer or more From an R...

Страница 8: ...n illustration consider a 50 ohm microstrip trace that is 18 mils wide over 10 mils of FR4 If that thickness of FR4 is changed from 10 to 6 mils the impedance will only be about 36 ohms In any case th...

Страница 9: ...we may consider that a metal trace on a PCB such as the QN9090 001M1x modules is approximately 0 8 nH per mm At lower frequencies this would have no impact but at 2 4 GHz this would have a significant...

Страница 10: ...been placed between the RFIO port of the chip and the first shunt capacitor These elements transform the device impedance to 50 ohms The value of these components may vary depending on your specific b...

Страница 11: ...r Murata GRM1555 type The same is true of inductors There is parasitic capacitance in an inductor mainly due to capacitive coupling between the turns of wire At some point in frequency this capacitanc...

Страница 12: ...finger that is not connected to the ground reference with a via put a via in any trace that doesn t go anywhere 4 7 Layers interconnections Avoid vias in the RF traces Typically for a 1 6mm thickness...

Страница 13: ...ference is specified and built correctly to ensure that the system functions properly The choice of crystal resonator is important for the following reasons Resonator tolerance A number of parameters...

Страница 14: ...ents is not recommended as this may lead to both oscillator start up and frequency tolerance issues 4 10 Decoupling 4 10 1 General considerations Decouple the power supplies or regulated voltages as c...

Страница 15: ...capacitors placement 4 10 2 VDD RADIO FB VDD_PMU VDDE and VBAT decoupling Copy as much as possible the placement of the decoupling capacitors of all the supply pins as shown below Fig 10 VDD Radio de...

Страница 16: ...ough the capacitor created by these traces In order to minimize the effect of this parasitic coupling identify the most sensitive traces or areas RF trace oscillator power lines and separate them from...

Страница 17: ...hen mounting this module onto another PCB The area around the antenna must be kept clear of conductors or other metal objects for an absolute minimum of 20 mm This is true for all layers of the PCB an...

Страница 18: ...ce manual Rev 1 0 17 Jan 2020 18 of 31 Fig 14 PCB placement of a QN9090 module with a printed antenna 6 Manufacturing considerations The HVQFN package must be considered carefully when using reflow so...

Страница 19: ...pad stacks used are 0 25 mm by 1 mm for the smaller pads and four 1 6 mm square pads to apply paste to the paddle The solder paste mask has a thickness of 6 thou 0 152 mm If the paste thickness needs...

Страница 20: ...ual Rev 1 0 17 Jan 2020 20 of 31 Fig 17 Solder paste mask for HVQFN40 40 pin QFN Fig 18 Vias on the paddle of the HVQFN40 40 pin QFN 25 vias are applied to the paddle These allow excess solder paste a...

Страница 21: ...ment Directive 2014 53 EU a Frequency bands in which the equipment operates b The maximum RF power transmitted PN RF Technology a Freq Ranges EU b Max Transmitted Power QN9090 001 T10 Bluetooth LE 240...

Страница 22: ...ponents that had not previously used for such applications 1 4 Have the non standard components been qualified so that they can be used in the application 1 5 Are recommendations for layout form facto...

Страница 23: ...has not been recommended by NXP have all the parameters been checked in order they fulfill NXP standard and application requirements load capacitance pulling sensitivity equivalent resistance frequen...

Страница 24: ...from the pin for sensitivity measurements 8 5 For printed and chip antenna Is the RF line implemented in such a way that the HW can be easily modified in order to do conducted measurements on one han...

Страница 25: ...4 Has the correct PCB material been specified 1 5 Have the correct PCB thicknesses been specified 2 RF IO 2 1 Is the RF_IO input output line well sized for 50 ohm The line width must be calculated acc...

Страница 26: ...ed does one layer act as a continuous ground plane GND reference plane 5 2 Are numerous vias added near capacitor near fingers 5 3 Remove small GND areas and isolated fingers that cannot be connected...

Страница 27: ...Abbreviations Table 4 Abbreviations Acronym Description EMC Electro Magnetic Compatibility ETSI European Telecommunications Standards Institute FCC Federal Communications Commission PAN Personal Area...

Страница 28: ...CB stack up 8 Fig 5 RF Matching Network 10 Fig 6 RF Plots for 3pF ceramic capacitor Murata GRM1555 type 11 Fig 7 GND path between C10 C12 and C19 13 Fig 8 GND vias placement 14 Fig 9 Decoupling capaci...

Страница 29: ...ovided in this document is subject to legal disclaimers NXP Semiconductors N V 2020 All rights reserved Reference manual Rev 1 0 17 Jan 2020 29 of 31 13 List of tables Table 1 Modules references 4 Tab...

Страница 30: ...rint 6 4 2 PCB Stack Up 7 4 3 RF circuit topology and matching 9 4 4 Transmission lines 9 4 5 Components 10 4 6 GND planes 12 4 7 Layers interconnections 12 4 8 DCDC components 12 4 9 Reference Oscill...

Страница 31: ...cations and products and NXP accepts no liability for any vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks associated with...

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