NXP Semiconductors
QN902x
User Manual of QN902x
UM10996
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© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev 1.3
— 05 November 2018
77 of 128
The SPI master can connect to two slave devices, and select one slave device to
communicate by setting MSTR_SSx(CR0[14:15]). Only one slave device should be selected
at a time.
10.2.2
Slave Mode Operation
The SPI interface is programmed as a slave device by setting SPI_MODE to 1. If the slave
is selected by a master device via nCS, the data are shifted in through the DIN pin and out
through the DAT pin, clocked by the SCK signal from the master device. The slave device
cannot initiate the data transfer. Data to be transferred to the master device is pre-loaded
into the TX buffer by writing to TXD.
10.2.3
Timing
SPI master support 4 modes, the timing diagram is the same for master and slave as
follows.
CPOL = 0
CPOL = 1
SCK
SS
Cycle #
Data Out
Data In
Cycle #
Data Out
Data In
CPHA=1
CPHA=0
Data captured at the SCK leading edge
Data propagated at the SCK trailing edge
1
2
3
4
5
6
7
8
1
Z
Z
2
3
4
5
6
7
8
1
Z
Z
2
3
4
5
6
7
8
2
3
4
5
6
7
8
1
Z
Z
2
3
4
5
6
7
8
1
Z
Z
2
3
4
5
6
7
8
1
Data propagated at the SCK leading edge
Data captured at the SCK trailing edge
The CPOL defines the logic level when the SPI is idle, while the CPHA defines the active
edge of the SCK to capture the input data.
The SS signal is active low and asserted when the data transfer is initiated by the master
device. It is de-asserted when no more data is in the Tx buffer of master and that last bit
in the shift register is sent out.
10.2.4
Clock generation
The SPI clock is derived by diving the AHB clock as follows:
- USARTx_DIV_BYPASS=1, SPI_CLK=AHB_CLK
- USARTx_DIV_BYPASS=0, SPI_CLK=AHB_CLK/(2*(USARTx_DIVIDER[2:0]+1))
In the master mode, the SCK is generated from the SPI_CLK as shown below:
SCK=SPI_CLK/(2*(BITRATE[5:0]+1))
