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Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
18-14 Freescale Semiconductor
Table 18-10. MPU_RGDAACn Field Descriptions
Field Description
M6RE Bus Master ID 6 Read Enable. If set, this flag allows bus master ID (FlexRay) 6 to perform read operations. If cleared,
any attempted read by bus master ID 6 terminates with an access error and the read is not performed.
M6WE Bus Master ID 6 Write Enable. If set, this flag allows bus master ID 6 (FlexRay) to perform write operations. If cleared,
any attempted write by bus master ID 6 terminates with an access error and the write is not performed.
M5RE Bus Master ID 5 Read Enable. If set, this flag allows bus master ID 5 (Media Local Bus) to perform read operations.
If cleared, any attempted read by bus master ID 5 terminates with an access error and the read is not performed.
M5WE Bus Master ID 5 Write Enable. If set, this flag allows bus master ID 5 (Media Local Bus) to perform write operations.
If cleared, any attempted write by bus master ID 5 terminates with an access error and the write is not performed.
M4RE Bus Master ID 4 Read Enable. If set, this flag allows bus master ID (FEC) 4 to perform read operations. If cleared,
any attempted read by bus master ID 4 terminates with an access error and the read is not performed.
M4WE Bus Master ID 4 Write Enable. If set, this flag allows bus master ID 4 (FEC) to perform write operations. If cleared,
any attempted write by bus master ID 4 terminates with an access error and the write is not performed.
M2PE This bit can be read and written to either a 0 or 1, but the MPU behaves as if this bit was permanently tied to 0, so
that the PID is not part of the region hit evaluation.
M2SM Bus Master 2 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master ID 2
(eDMA) when operating in supervisor mode. The M2SM field is defined as:
00
r, w, x =
read, write and execute allowed.
01
r, –, x =
read and execute allowed, but no write.
10
r, w, – =
read and write allowed, but no execute.
11 Same access controls as that defined by M2UM for user mode.
M2UM Bus Master 2 User Mode Access Control. This 3-bit field defines the access controls for bus master ID 2 (eDMA)
when operating in user mode. The M2UM field consists of three independent bits, enabling read, write, and execute
permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that
mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed.
M1PE Bus Master 1 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, the region hit evaluation does not
include the process identifier.
M1SM Bus Master 1 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master ID 1
(e200z0) when operating in supervisor mode. The M1SM field is defined as:
00
r, w, x =
read, write and execute allowed.
01
r, –, x =
read and execute allowed, but no write.
10
r, w, – =
read and write allowed, but no execute.
11 Same access controls as that defined by M1UM for user mode.
M1UM Bus Master 1 User Mode Access Control. This 3-bit field defines the access controls for bus master ID 1 (e200z0)
when operating in user mode. The M1UM field consists of three independent bits, enabling read, write, and execute
permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that
mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed.
M0PE Bus Master 0 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not
include the process identifier.