NXP Semiconductors PXN2020, Справочное руководство, Страница: 176 / 1376

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
7-14 Freescale Semiconductor
much the two clocks lead or lag each other. After phase lock is achieved, the PFD continues to pulse the
UP and DOWN signals for a very short duration during each reference clock cycle. These short pulses
force the PLL to continually update and prevent a frequency drift phenomena referred to as
“dead-banding.” Dead-band describes the minimum amount of phase error between the reference and
feedback clocks that a phase detector cannot correct.
7.4.3.3.2 Charge Pump/Loop Filter
Operation of the charge pump is controlled by the UP and DOWN signals from the PFD. They control
whether the charge pumps apply or remove charge, respectively, from the loop filter.
7.4.3.3.3 VCO
The voltage into the VCO controls the frequency of its output. The frequency-to-voltage relationship
(VCO gain) is positive.
7.4.3.3.4 EMFD
The MFD divides down the output of the VCO and feeds it back to the PFD. The PFD controls the VCO
frequency (via the charge pump and loop filter) such that the reference and feedback clocks have the same
frequency and phase. Thus, the input to the MFD, which is also the output of the VCO, is at a frequency
that is the reference frequency multiplied by the same amount the MFD divides by. For example, if the
MFD divides the VCO frequency by 48, then the PLL is frequency locked when the VCO frequency is 48
times the reference frequency. The presence of the MFD in the loop allows the PLL to perform frequency
multiplication, or synthesis.
7.4.3.3.5 Programming System Clock Frequency
In normal PLL clock mode, the default system frequency is determined by the default EPREDIV, EMFD,
and ERFD values.
When programming the PLL, do not violate the maximum system clock frequency or max/min VCO
frequency specifications. Based on the desired system clock frequency, EPREDIV, EMFD, and ERFD
must be calculated for the given crystal or external reference frequency. See
PXN20 Microcontroller Data
Sheet for the max/min VCO frequency range and the maximum allowable system frequency.
Frequency modulation should be disabled prior to changing the EPREDIV, EMFD, or RATE bit fields.
After enabling frequency modulation a new calibration sequence is performed. A change to EPREDIV,
EMFD, DEPTH, or RATE while modulation is enabled invalidates the previous calibration results.
Use these directions to accommodate the frequency overshoot that occurs when the EPREDIV or EMFD
bits are changed. If frequency modulation is going to be enabled the maximum allowable frequency must
be reduced by the programmed

F
m
.
1. Determine the appropriate value for the EPREDIV, EMFD, and ERFD fields in the synthesizer
control register(s), remember to include the

F
m
if frequency modulation is to be enabled. The
amount of jitter in the system clocks can be minimized by selecting the maximum EMFD factor
that can be paired with an ERFD factor to provide the desired frequency. The maximum EMFD
value that can be used is determined by the VCO and EMFD range.