NXP Semiconductors
UM191812
PN544 C2 User Manual
191812
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User Manual
Rev. 1.2 — 2010-06-16
9 of 172
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CPOL and CPHA are part of SPI Configuration. For more information about these 2
parameters, please refer to following table:
Table 3.
CPOL / CPHA description
Bit name
description
CPOL Clock
polarity:
selects the polarity of the shift clock
1: shift clock is active low.
0: shift clock is active high.
CPHA
Clock phase:
This bit indicates, at which edge of the clock signal the data will be sampled. The
other edge initiates the value change on the data line
1: As soon as input pin NSS goes low, the transaction begins and the edge of SCK
invokes the first data sample. Sampling of the data happens at the even edges (2,
4…16) of the SCK clock.
0: if input pin NSS goes low, the outputs are enabled. Sampling of the data happens
at the odd edges (1, 3…15) of the SCK clock.
Table 4.
Pin functional description
Here is the functional description of each pins used by all interfaces
Pin Name
Dir
Description
RX
I
Asynchronous UART receiver input, which is similar to an RS232 protocol on
PVDD level.
TX
O
Asynchronous UART transmitter output which is similar to an RS232
protocol on PVDD level.
ADDR0 I
I
2
C slave address bit 0 (LSB)
ADDR1 I
I
2
C slave address bit 1
SDA
IO IO pin SDA
SCL
I
Clock Input pin SCL
NSS
I
Slave select active low for SPI slave mode
MOSI
I
Master Out Slave In
Data input pin in slave operation
SCK
I
Clock input pin in slave operation
MISO
O
Master In Slave Out
Data output pin in slave operation