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UM10346_1

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 01 — 2 November 2009

70 of 132

NXP Semiconductors

UM10346

LPC980/982 User manual

11.4 I

2

C Status register

This is a read-only register. It contains the status code of the I

2

C interface. The least three

bits are always 0. There are 26 possible status codes. When the code is F8H, there is no
relevant information available and SI bit is not set. All other 25 status codes correspond to
defined I

2

C states. When any of these states entered, the SI bit will be set. Refer to

for details.

11.5 I

2

C SCL duty cycle registers I2SCLH and I2SCLL

When the internal SCL generator is selected for the I

2

C interface by setting CRSEL = 0 in

the I2CON register, the user must set values for registers I2SCLL and I2SCLH to select
the data rate. I2SCLH defines the number of PCLK cycles for SCL = high, I2SCLL defines
the number of PCLK cycles for SCL = low. The frequency is determined by the following
formula:

Bit Frequency = f

PCLK

/ (2*( I2SCLL))

Where f

PCLK

is the frequency of PCLK.

3

SI

I

2

C Interrupt Flag. This bit is set when one of the 25 possible I

2

C states is entered.

When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI
is set. Must be cleared by software by writing 0 to this bit.

4

STO

STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the
I

2

C-bus. When the bus detects the STOP condition, it will clear STO bit

automatically. In slave mode, setting this bit can recover from an error condition. In
this case, no STOP condition is transmitted to the bus. The hardware behaves as
if a STOP condition has been received and it switches to ‘not addressed’ Slave
Receiver Mode. The STO flag is cleared by hardware automatically.

5

STA

Start Flag. STA = 1: I

2

C-bus enters master mode, checks the bus and generates a

START condition if the bus is free. If the bus is not free, it waits for a STOP
condition (which will free the bus) and generates a START condition after a delay
of a half clock period of the internal clock generator. When the I

2

C interface is

already in master mode and some data is transmitted or received, it transmits a
repeated START condition. STA may be set at any time, it may also be set when
the I

2

C interface is in an addressed slave mode. STA = 0: no START condition or

repeated START condition will be generated.

6

I2EN

I

2

C Interface Enable. When set, enables the I

2

C interface. When clear, the I

2

C

function is disabled.

7

-

reserved

Table 60.

I

2

C Control register (I2CON - address D8h) bit description

…continued

Bit Symbol

Description

Table 61.

I

2

C Status register (I2STAT - address D9h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

STA.4

STA.3

STA.2

STA.1

STA.0

0

0

0

Reset

0

0

0

0

0

0

0

0

Table 62.

I

2

C Status register (I2STAT - address D9h) bit description

Bit Symbol

Description

0:2 -

Reserved, are always set to 0.

3:7 STA[0:4] I

2

C Status code.

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Содержание P89LPC980

Страница 1: ...UM10346 LPC980 982 User manual Rev 01 2 November 2009 User manual Document information Info Content Keywords P89LPC980 982 Abstract Technical information for the P89LPC980 982 device...

Страница 2: ...009 2 of 132 Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM10346 LPC980 982 User...

Страница 3: ...rporated into the P89LPC980 982 in order to reduce component count board space and system cost 1 1 Pin configuration Fig 1 P89LPC980 982 TSSOP28 pin configuration P89LPC980 P89LPC982 002aae536 1 2 3 4...

Страница 4: ...2EX P1 0 TXD Table 1 Pin description Symbol Pin Type Description PLCC28 TSSOP28 P0 0 to P0 7 I O Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are...

Страница 5: ...I O P0 3 Port 0 bit 3 High current source I CIN1B Comparator 1 positive input B I KBI3 Keyboard input 3 I O T2 Timer counter 2 external count input or overflow output P0 4 CIN1A KBI4 23 I O P0 4 Port...

Страница 6: ...I O P1 1 Port 1 bit 1 I RXD Receiver input for serial port I T2EX Timer counter 2 external capture input P1 2 SCL T0 12 I O P1 2 Port 1 bit 2 open drain when used as output I O T0 Timer counter 0 ext...

Страница 7: ...ut When configured as master this pin is input when configured as slave this pin is output P2 4 SS 15 I O P2 4 Port 2 bit 4 I SS SPI Slave select P2 5 SPICLK 16 I O P2 5 Port 2 bit 5 I O SPICLK SPI cl...

Страница 8: ...nternal clock generator circuits when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are...

Страница 9: ...ymbols 1 For Pin Remap Fig 3 P89LPC980 982 logic symbol VDD VSS PORT 0 PORT 3 TXD RXD T0 INT0 INT1 RST SCL SDA 002aae534 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2 XTAL1 KBI0 SPICLK 1 T2 T3 KBI...

Страница 10: ...OGRAMMABLE OSCILLATOR DIVIDER CPU clock CONFIGURABLE OSCILLATOR ON CHIP RC OSCILLATOR WITH CLOCK DOUBLER internal bus POWER MANAGEMENT POWER ON RESET BROWNOUT RESET REGULATORS 002aae532 UART ANALOG CO...

Страница 11: ...SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specif...

Страница 12: ...ctions and addresses Reset value MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator E0H 00 0000 0000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 DPS 00 0000 0...

Страница 13: ...DR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 Bit address DF DE DD DC DB DA D9 D8 I2CON I2C bus control register D8H I2EN STA STO SI AA CRSEL 00 x000 00x0 I2DAT I2C bus data register DAH I2SCLH Serial...

Страница 14: ...pt mask register 86H 00 0000 0000 KBPATN Keypad pattern register 93H FF 1111 1111 Bit address 87 86 85 84 83 82 81 80 P0 Port 0 80H T1 KB7 CMP1 KB6 CMPREF KB5 T3 CIN1A KB4 CIN1B KB3 T2 CIN2A KB2 CIN2B...

Страница 15: ...rt 3 output mode 1 B1H P3M1 1 P3M1 0 03 1 xxxx xx11 P3M2 Port 3 output mode 2 B2H P3M2 1 P3M2 0 00 1 xxxx xx00 PCON Power control register 87H SMOD1 SMOD0 BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000 PCONA Po...

Страница 16: ...ee Cycle Register 4 High Byte AAH 00 0000 0000 PWMD4L PWM Free Cycle Register 4 Low Byte ABH 00 0000 0000 RCAP2H Capture Register 2 High Byte FCH 00 0000 0000 RCAP2L Capture Register 2 Low Byte FBH 00...

Страница 17: ...I RI 00 0000 0000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 SP Stack pointer 81H 07 0000 0111 SPCTL SPI control register E2H SSIG SPEN DORD MS...

Страница 18: ...e cleared except POF and BOF the power on reset value is x011 0000 TH2 Timer Counter 2 High Byte FEH 00 0000 0000 TL2 Timer Counter 2 Low Byte FDH 00 0000 0000 T3CON Timer Counter 3 Control EFH PSEL3...

Страница 19: ...itialization of the TRIM register 6 The only reset sources that affect these SFRs are power on reset and watchdog reset 1 Extended SFRs are physically located on chip but logically located in external...

Страница 20: ...than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and perip...

Страница 21: ...can also be optionally divided to a slower frequency see Figure 7 and Section 2 10 CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the D...

Страница 22: ...he clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore wh...

Страница 23: ...scillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM 0 Reset 0 0 Bits 5 0 loaded with factory stored value during rese...

Страница 24: ...ency crystals see text 2 C1 and C2 are suggested to be equal in middle speed oscillator or high speed oscillator mode Higher capacitance is required on C1 in low speed oscillator mode For example when...

Страница 25: ...Symbol CLKOK WDMOD XTALWD CLKDBL FOSC2 FOSC1 FOSC0 Reset 1 0 0 0 x x x x Table 8 Clock control register CLKCON address FFDEh bit description Bit Symbol Description 2 0 FOSC2 FOSC1 FOSC0 CPU oscillato...

Страница 26: ...g at 8 MHz or slower 3 Interrupts The P89LPC980 982 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC980 982 s 14 interrupt sources...

Страница 27: ...e and then hold it low for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the serv...

Страница 28: ...2 IP0 2 7 Yes Timer 1 interrupt TF1 001Bh ET1 IEN0 3 IP0H 3 IP0 3 10 No Serial port Tx and Rx TI and RI 0023h ES ESR IEN0 4 IP0H 4 IP0 4 13 No Serial port Rx RI Brownout detect BOIF 002Bh EBO IEN0 5...

Страница 29: ...set options chosen see Table 12 Fig 8 Interrupt sources interrupt enables and power down wake up sources 002aae983 IE0 EX0 IE1 EX1 BOIF EBO KBIF EKBI interrupt to CPU wake up if in power down EWDRT CM...

Страница 30: ...pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the...

Страница 31: ...sheet Dynamic characteristics for glitch filter specifications 4 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor...

Страница 32: ...has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may...

Страница 33: ...l inputs disabled will be read as 0 by any instruction that accesses the port On any reset PT0AD bits 1 through 5 default to logic 0s to enable the digital functions 4 7 Additional port features After...

Страница 34: ...ing PINCON register according to the application Refer to Table 16 and Table 17 for details Table 14 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P0 0...

Страница 35: ...d in normal or idle mode through configuring regulators mode according to the applications 5 1 Brownout detection The brownout detect function determines if the power supply voltage drops below a cert...

Страница 36: ...rrupt is enabled by setting BOI PCON 4 bit Please refer to Table 20 for BOD reset and BOD interrupt configuration BOF bit RSTSRC 5 BOD reset flag is default as 0 and is set when BOD reset is tripped B...

Страница 37: ...oftware 5 3 Power reduction modes The P89LPC980 982 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 21 Table 19 BOD interrupt Trip points configuration BOIC...

Страница 38: ...uation VDD must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin executi...

Страница 39: ...efore being supplied to the UART See Section 10 UART Table 24 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD VCPD I2PD SPPD SPD Reset 0 x 0 x 0 0 0 x Table...

Страница 40: ...he external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power on sequence The RPE selection is overridden and this pin will always functions as a reset i...

Страница 41: ...UCFG2 7 watchdog timer reset software reset SRST AUXR1 3 power on detect UART break detect EBRR AUXR1 6 brownout detect reset chip reset 002aae587 Table 28 Reset Sources register RSTSRC address DFh bi...

Страница 42: ...aximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes...

Страница 43: ...ounter is enabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set Table 32 Timer Counter Auxiliary Mode register TAMOD ad...

Страница 44: ...Ln with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 7 4 Mode 3 When Timer 1 is in Mode 3 it is stopped The...

Страница 45: ...Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 3 IE1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detec...

Страница 46: ...in toggle overflow interrupt Fig 16 Timer counter 0 or 1 in Mode 2 8 bit auto reload 002aaa921 PCLK Tn pin TRn Gate INTn pin C T 0 C T 1 TLn 8 bits THn 8 bits TFn control ENTn Tn pin toggle overflow i...

Страница 47: ...T3 T4 The count input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register d...

Страница 48: ...x x 0 0 0 0 0 0 Table 39 Timer Counters Overflow and External Flags TINTF address CEh bit description Bit Symbol Description 0 EXF2 Timer 2 external flag This bit is set when a capture or reload is t...

Страница 49: ...transition also sets the EXFx bit It takes two consecutive machine cycles to recognize falling edge on TxEX and another one machine cycle to set EXFx The Timer x interrupt if enabled can be generated...

Страница 50: ...nsition at TxEX will set EXFx bit in TINTF EXFx bit like TFx bit can generate an interrupt which vectors to the same location as Timer x overflow interrupt The Timer x interrupt service routine can ch...

Страница 51: ...ng in PWM mode Its structure is similar to auto reload mode except that TFx where x 2 3 or 4 is set and cleared in hardware The high period of the TFx is in RCAPxH RCAPxL and the low period of TFx is...

Страница 52: ...be an interrupt or a wake up source see Figure 23 The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or the XTAL1 2 oscillator There are f...

Страница 53: ...1 RTCS0 9 3 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IEN0 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog...

Страница 54: ...00 Medium frequency crystal Medium frequency crystal DIVM 01 10 11 Medium frequency crystal DIVM 1 00 Medium frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 010 0 00 Low freq...

Страница 55: ...43 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this b...

Страница 56: ...he baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection 10 3 Mode 2 11 bits are transmitted through TXD or...

Страница 57: ...an interim value to the baud rate generator CAUTION If either BRGR0 or BRGR1 is written when BRGEN 1 the result is unpredictable Table 44 UART SFR addresses Register Description SFR location PCON Powe...

Страница 58: ...nerator Enable Enables the baud rate generator BRGR1 and BRGR0 can only be written when BRGEN 0 1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and 3 see Table 45 fo...

Страница 59: ...ny reset 01 Mode 1 8 bit UART Variable see Table 45 10 Mode 2 9 bit UART CCLK 32 or CCLK 16 11 Mode 3 9 bit UART Variable see Table 45 Table 51 Serial Port Status register SSTAT address BAh bit alloca...

Страница 60: ...perations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is disabled Note that except for the first character writ...

Страница 61: ...ooking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will p...

Страница 62: ...th data bit goes into RB8 and the first 8 data bits go into SBUF 10 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table Fig 26 Ser...

Страница 63: ...be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out 10 16 Doub...

Страница 64: ...Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit o...

Страница 65: ...ill occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out t...

Страница 66: ...p to show the versatility of this scheme In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Sl...

Страница 67: ...tic purposes A typical I2C bus configuration is shown in Figure 29 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus Data transfer from a master t...

Страница 68: ...s located at the MSB of I2DAT 11 2 I2C slave address register I2ADR register is readable and writable and is only used when the I2C interface is set to slave mode In master mode this register has no e...

Страница 69: ...ition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits a STA...

Страница 70: ...dition is transmitted to the I2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP...

Страница 71: ...set to 1 to enable the I2C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can no...

Страница 72: ...bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or 0B0h if the slave mode was enabled setting AA Logic 1 The appropriate a...

Страница 73: ...data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code c...

Страница 74: ...ested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arb...

Страница 75: ...BUS 002aaa899 ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 I2ADR ACK BIT COUNTER ARBITRATION SYNC LOGIC 8 I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAG...

Страница 76: ...T action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W...

Страница 77: ...eiver mode Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI STA 08H A START condition has been transmitte...

Страница 78: ...TA STO SI AA 60H Own SLA W has been received ACK has been received no I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will be returned no I2DAT action x 0 0 1 Data byte will be received...

Страница 79: ...has been received ACK has been returned Read data byte or x 0 0 0 Data byte will be received and NOT ACK will be returned read data byte x 0 0 1 Data byte will be received and ACK will be returned 98H...

Страница 80: ...omes free Table 68 Slave Receiver mode continued Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI AA Tabl...

Страница 81: ...will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A STA...

Страница 82: ...abled i e SPEN SPCTL 6 0 reset value If the SPI is configured as a master i e MSTR SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits If the SS pin is ignored i e SSIG SP...

Страница 83: ...e data word is transmitted first 0 The MSB of the data word is transmitted first 6 SPEN SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 SSIG SS IGnore 1 MSTR...

Страница 84: ...figured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 12 4 Mode change on SS...

Страница 85: ...BIT SHIFT REGISTER SPI CLOCK GENERATOR 8 BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS slave 8 BIT SHIFT REGISTER MISO MOSI SPICLK SS Table 75 SPI master and slave selection SPEN S...

Страница 86: ...ow Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out o...

Страница 87: ...t to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causin...

Страница 88: ...UM10346 LPC980 982 User manual 1 Not defined Fig 40 SPI slave transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2...

Страница 89: ...UM10346 LPC980 982 User manual 1 Not defined Fig 41 SPI slave transfer format with CPHA 1 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2...

Страница 90: ...UM10346 LPC980 982 User manual 1 Not defined Fig 42 SPI master transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MS...

Страница 91: ...r an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes 13 1 Comparator configuration Each comparator has a...

Страница 92: ...r interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software 1 COn Comparator output synchroniz...

Страница 93: ...CIN1A P0 3 CIN1B P0 5 CMPREF Vref cmp 1 OE1 change detect CO1 CMF1 interrupt 002aac346 CMP1 P0 6 EC change detect CMF2 comparator 2 OE2 CO2 CMP2 P0 0 CP2 CN2 P0 2 CIN2A P0 1 CIN2B Table 78 Comparator...

Страница 94: ...s will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the com...

Страница 95: ...030h Disable digital INPUTS on CIN1A CMPREF ANL P0M2 0CFh Disable digital OUTPUTS on pins that are used ORL P0M1 030h for analog functions CIN1A CMPREF MOV CMP1 024h Turn on comparator 1 and set up f...

Страница 96: ...ing the EKBI bit in IEN1 register and EA 1 The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt...

Страница 97: ...owed by a feed sequence see Section 15 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler Table 83 Keypad Control register KBCON address 94h bit descrip...

Страница 98: ...dog reset when the watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take...

Страница 99: ...nce assumes that the P89LPC980 982 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the...

Страница 100: ...WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 15 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed...

Страница 101: ...w clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy cou...

Страница 102: ...bit If IEN0 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded int...

Страница 103: ...is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of t...

Страница 104: ...anipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC980 982 since the...

Страница 105: ...commercial programmers In Circuit serial Programming ICP with industry standard commercial programmers IAP Lite allows individual and multiple bytes of code memory to be used for data storage and pro...

Страница 106: ...e status bits are cleared to logic 0s when the command is written FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify...

Страница 107: ...OAD command 00H to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags Write the address within the page register to FMADRL Since the loading the...

Страница 108: ...a to page register INC R0 point to next byte DJNZ R3 LOAD_PAGE do until count is zero MOV FMCON EP else erase program the page Table 94 Flash Memory Control register FMCON address E4h bit description...

Страница 109: ...ge register enable loading define EP 0x68 erase program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page_hi FMADRL page_lo write my page address to addr regs for i 0...

Страница 110: ...clude operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FF00 to FFFFh thereby not...

Страница 111: ...med to zero in order to allow execution of the user s application code beginning at address 0000H 17 10 In system programming ISP In System Programming is performed without removing the microcontrolle...

Страница 112: ...is a data record A record type of 01 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum numbe...

Страница 113: ...6070809DC3 01 Read Version Id 00xxxx01cc Where xxxx required field but value is a don t care cc checksum Example 00000001FF 02 Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field bu...

Страница 114: ...1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 10 Manufacturer Id 11 Device Id 12 Derivative Id Example 0100000312EA 04 Erase Sect...

Страница 115: ...gm_mtp void 0xFF00 set pointer to IAP entry point key 0x96 set the authorization key pgm_mtp execute the IAP function call After the function call is processed by the IAP routine the authorization key...

Страница 116: ...e Configuration Write Protect bit CWP is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configur...

Страница 117: ...settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may b...

Страница 118: ...F1 0h use IDATA Return parameter s R7 status Carry set on error clear on no error Read Version Id Input parameters ACC 01h Return parameter s R7 IAP version id Misc Write requires key Input parameters...

Страница 119: ...ity Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 Return parameter s R7 register data if no error else error status Carry set...

Страница 120: ...lear on no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on erro...

Страница 121: ...FG1 bit description continued Bit Symbol Description Table 101 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator nominal 400 kHz 25...

Страница 122: ...s EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation i...

Страница 123: ...le CWE commands 6 CWP Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 UCFG2 BOOTVEC and BOOTSTAT If programmed to a logic 1 the writes to...

Страница 124: ...1 1 96 to 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect mem...

Страница 125: ...Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir R...

Страница 126: ...12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative addr...

Страница 127: ...time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or w...

Страница 128: ...h bit description 43 Table 34 Timer Counter Control register TCON address 88h bit allocation 45 Table 35 Timer Counter Control register TCON address 88h bit description 45 Table 36 Timer Counter x Con...

Страница 129: ...ion 98 Table 87 Watchdog Timer Control register WDCON address A7h bit allocation 100 Table 88 Watchdog Timer Control register WDCON address A7h bit description 100 Table 89 Watchdog timeout vales desi...

Страница 130: ...Baud rate generation for UART Modes 1 3 58 Fig 25 Serial Port Mode 0 double buffering must be disabled 61 Fig 26 Serial Port Mode 1 only single transmit buffering case is shown 62 Fig 27 Serial Port M...

Страница 131: ...ode 0 16 bit Timer Counter with Auto reload 49 8 2 Mode 1 16 bit Timer Counter with Input Capture 50 8 3 Mode 2 16 bit PWM mode 51 8 4 Timer overflow toggle output 52 9 Real time clock system timer 52...

Страница 132: ...odic wake up from power down without an external oscillator 103 16 Additional features 103 16 1 Software reset 104 16 2 Dual Data Pointers 104 17 Flash memory 105 17 1 General description 105 17 2 Fea...

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