UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
46 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
7.
Reset
The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input
with an internal pullup, a bidirectional reset input/output (open drain output with an internal
pullup), or as push-pull reset output. These modes are selected by the RPE (Reset Pin
Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.
Remark:
During a power-up sequence, The RPE and RPE1 selection is overridden and
this pin always functions as a reset input.
An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset.
After power-up this pin will function as defined by the RPE and RPE1
bits. Only a power-up reset will temporarily override the selection defined by RPE and
RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.
Note:
During a power cycle, V
DD
must fall below V
POR
(see
P89LPC952/954 data sheet,
Static characteristics
) before power is reapplied, in order to ensure a power-on reset.
Note:
When using an oscillator frequency above 12 MHz, the reset input function of P1.5
must be enabled. An external circuit is required to hold the device in reset at power-up
until V
DD
has reached its specified level. When system power is removed V
DD
will fall
below the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may be required
to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
Reset can be triggered from the following sources:
•
External reset pin (during power-up or if user configured via UCFG1, UCGF2);
•
Power-on detect;
•
Brownout detect;
•
Watchdog timer;
•
Software reset;
•
UART break character detect reset.
5
VCPD
Analog Voltage Comparators power-down: When logic 1, the voltage comparators
are powered down. User must disable the voltage comparators prior to setting this
bit.
6
DEEPD
Data EEPROM power-down: When logic 1, the Data EEPROM is powered down.
Note that in either Power-down mode or Total Power-down mode, the Data
EEPROM will be powered down regardless of this bit.
7
RTCPD
Real-time Clock power-down: When logic 1, the internal clock to the Real-time
Clock is disabled.
Table 31.
Power Control register A (PCONA - address B5h) bit description
…continued
Bit
Symbol
Description
Table 32.
Reset pin modes
P1.5/RST mode
RPE1 (UCFG2.0) RPE (UCFG1.6)
General purpose input
0
0
Reset input with pullup
0
1
Bidirectional reset input/output (open drain with pullup)
1
0
Reset ouput
1
1
