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P5040/P5020 Reference Design Board User Guide, Rev. 0

Freescale Semiconductor

Programming Model

7.1.6

Clock Enable Register (PX_SERCLK)

This section outlines the clock enable register.

Figure 27. Clock Enable Register (PX_SERCLK)

Table 31. PX_RST Field Descriptions

Bits

Name

Description

ALL

Resets the entire system.
• 0 - Initiates a full system reset.
• 1 - Normal operation

1–3

—

Reserved

SXSLOT

Resets any board connected via the SGMII/XAUI riser card slot.
• 0 - SXSLOT_RST_B is asserted.
• 1 - SXSLOT_RST_B is deasserted.

PHY

Resets 10/100/1G Ethernet PHY.
• 0 - PHY_RST_B is asserted.
• 1 - PHY_RST_B is deasserted.

—

Reserved

GEN

Resets miscellaneous board features; see schematics and/or documentation.
• 0 - GEN_RST_B is asserted.
• 1 - GEN_RST_B is deasserted.

PX_RST register bits cannot reset independently.

PX_RST[ALL] only resets during a full system reset. Bits [1-7] must be cleared with software.

SERCLK_EN

SDREFCLK1_

SDREFCLK2_

SDREFCLK3_

USBCLK_EN

SDREFCLK4_

—

Reset

---

The Default depends on chip: For P5040 =’1’, otherwise ‘0’;

Offset

0x05

Table 32. PX_SERCLK Field Descriptions

Bits

Name

Description

SDREFCLK1_QA_EN

Enables/disables the SerDes Reference Clock to Bank 1 and Slot 1
• 0 - disabled
• 1 - enabled

SDREFCLK1_QB_EN

Enables/disables the SerDes Reference Clock to Aurora port and Slot 2
• 0 - disabled
• 1 - enabled

SDREFCLK2_QC_EN

Enables/disables the SerDes Reference Clock to Bank2 and XAUI PHY
• 0 - disabled
• 1 - enabled

Содержание P5010

Страница 1: ...sors implemented in this reference board The processors currently supported and the orderable part number for each kit are as follows P5040 P5021 P5040 RDB P5020 P5010 P5020 RDB 1 Before you begin Thi...

Страница 2: ...2 PHY supporting two XAUI copper link 10GHz and two XFI link supporting 10GHz modules Two SATA II connectors Two Gigabit Ethernet ports 0 and 1 supporting one dual RGMII 1 GHz RJ 45 Ethernet connector...

Страница 3: ...ee I2 C controllers from P5040 and P5020 I2 C1 to RCW Boot Sequencer and System configuration EEPROMs XAUI SFP ports 1 and 2 I2 C2 to DDR slots SPD I2 C3 to system real time clock and CPU Thermal Moni...

Страница 4: ...gn Board User Guide Rev 0 4 Freescale Semiconductor Block Diagram 3 Block Diagram This figure depicts the general features and connectivity of the P5040 P5020 reference board Figure 1 P5040 P5020 Refe...

Страница 5: ...essor Reference Board For general hardware and or software development and evaluation purposes the P5040 P5020 reference design board can be used like an ordinary desktop computer The P5040 P5020 refe...

Страница 6: ...capable of supporting DDR3 and DDR3 LV devices Provides 2 SODIMM slots with one DDR3 8GB 204 pin 1 35 1 5v SODIMM module at 1333 1600 Mbps data rate at 72 bit and ECC support eSDHC SDMedia card and MM...

Страница 7: ...3 Difficult to Find Connections P5040 P5020 reference board Top View 5 Architecture 5 1 Processor This table lists the major pin groupings of the P5040 P5020 Table 3 P5040 P5020 Pin Groupings Summary...

Страница 8: ...7 enhanced Secure Digital Host Controller eSDHC embedded Multi Media Controller eMMC SPI Section 5 1 6 enhanced Serial Peripheral Interface eSPI UART Serial Ports Section 5 1 8 UART Serial Ports USB...

Страница 9: ...Technology LTC3876 U55 switching power controller as follows Dual phase controller for up to 20 A at a default at 1 35 v adjustable to 1 5 V output Supplies GVDD VREF and VTT for SODIMM DRAM DDR3 and...

Страница 10: ...in the case of PCI Express or Serial RapidIO a lane consists of two differential pairs one for receive and one for transmit or four in all Table 5 top down shows the following clocking banks and how...

Страница 11: ...A2 PCIe1 5 2 5G SGMII FM2 SGMII FM2 SGMII FM2 SGMII FM2 Debug 5 2 5G XAUI FM1 SATA1 SATA2 Table 5 P5040 P5020 SerDes Lane Multiplexing Configurations on P5040 P5020 continued Bank 1 Bank 2 Bank 3 Bank...

Страница 12: ...5040 P5020 SerDes Bank1 to Reference Board Cards Debug Connector Configuration P5040 P5020 SD_TX RX 0 3 p n PEX Slot 1 TX RX 0 3 p n REFCLK_SD1 p n 100 MHz PEX Slot 2 TX RX 4 7 p n Aurora Conn TX RX 1...

Страница 13: ...ol This table shows the general organization of the ETH system Table 6 10 100 1000 Base T GETH Ports GETH Feature Specifics Description GETH Clocks IDT ICS8304AMLF Low skew Fanout Buffer Receives 125M...

Страница 14: ...port EMI1_MDC clock EMI1_MDIO bi directional data line MAX4906 Analog switch that chooses EMI1 routing EMI1 Routing determined by one of the following P5040 P5020 GPIO 0 3 ngPIXIS registers PX_BRDCFG...

Страница 15: ...ard EC connections and routing when the board is populated with a P5040 or P5020 processor See Section 5 1 9 USB Interfaces Table 7 P5040 P5020 Ethernet Port Locations on P5040 P5020 P5040 P5020 EC Co...

Страница 16: ...wn in Figure 9 This facility works in tandem with an Ethernet controller to timestamp incoming packets Figure 9 IEEE 1588 Interface to Reference Board Symmetricon Riser Connector 5 1 5 Serial Interfac...

Страница 17: ...has an eSPI Master Controller used to communicate with various peripherals Two SPI FLASH support 24 bit address and SPI Modes 0 3 Use Chip Select 0 or 1 with S25FL129P0XNFI001 FLASH if CVDD 3 3 V Use...

Страница 18: ...ge 5 1 8 UART Serial Ports Two RS 232 transceivers on the P5040 P5020RDB contribute to user application development and provide convenient communication channels to both terminal and host computers Th...

Страница 19: ...with keyboards mice memory sticks etc Working in Host and Device modes a second USB transceiver connects to a second Type A connector which has bus signal connecting directly to the P5040 P5020 intern...

Страница 20: ...0 DMA Controllers The P5040 P5020 DMA controllers have internal and external controls to initiate and monitor DMA activity The reference board does not incorporate any specific devices that make use o...

Страница 21: ...Legacy COP and Aurora connector resets are muxed to the ngPIXIS FPGA Table 10 P5040 P5020 Interrupt Assignments Signal Name Interrupt Source Description IRQ0_B IRQ1_B DS3232 U50 System RTC IRQ2_B Zilk...

Страница 22: ...set Sequence Table 12 PORESET Sequence Step Sequence Stage Description 1 PORESET General Information 1 PORESET is asserted 2 FPGA drives CFG_RCW_SRC 4 0 and all reset configuration input signals to P5...

Страница 23: ...a chosen configuration 4 Configuration Input Reset configuration inputs are sampled to determine the following Configuration source CFG_RCW_SRC 4 0 CFG_DBG_RST_DIS CFG_ENG_USE 3 0 CFG_PLL_CONFIG_SEL_...

Страница 24: ...Source Value Binary Reset Configuration Signal Name Description 0_0000 CFG_RCW_SRC 4 0 I2 C1 normal addressing supports ROMs up to 256 bytes 0_0001 I2 C1 extended addressing 0_0010 Reserved 0_0011 Re...

Страница 25: ...oot sequencer startup code if needed or Zilker Lab PM Bus programmer 2 0x51 DDR3 SODIMM Socket 1 SPD EEPROM Type of device depends on uDIMM vendor 2 0x52 DDR3 SODIMM Socket 2 SPD EEPROM Type of device...

Страница 26: ...C Scheme 4 n a I2 C Access Header For remote programming if needed 4 n a ngPIXIS I2C Port For bus reset monitoring and master only data collection 1 Map addresses do not include the position of a tra...

Страница 27: ...lexers are used to route from the P5040 P5020 to each SGMII and RGMII PHYs while EMI2_MDIO bus is routed to XAUI PHY See Section 7 Programming Model for details on using GPIO to select EMI1 device PHY...

Страница 28: ...P5040 P5020 Reference Design Board User Guide Rev 0 28 Freescale Semiconductor Architecture This figure shows the eLBC block diagram Figure 14 eLBC Interface...

Страница 29: ...he FLASH is controlled by the GPCM local bus Bus data is obtained from the data transceiver For address information see Section 5 1 16 1 Address Latch Data Transceivers FLASH functioning is as follows...

Страница 30: ...om CS0 or CS1 select between PromJet FLASH and onboard FLASH as per CFG_LBMAP 0 3 5 1 17 Debug Features The reference board provides a JTAG COP header and AURORA test points for debug purposes using t...

Страница 31: ...reset The ngPIXIS is implemented in an Actel A3P1000 FGG484 484 pad micro BGA This figure shows the overall ngPIXIS architecture Figure 15 FPGA Overview Main ngPIXIS features include the following Tab...

Страница 32: ...se modal operations 5 2 3 LOCALBUS LOCALBUS is the interface between processor and REGFILE asynchronous signaling is used since access to the internal registers may be blocked 5 2 4 REGISTERS REGFILE...

Страница 33: ...connected to individual power planes in the P5040 P5020RDB PCB stackup The 12 V power from the standard 1U header is treated as separate from the 1U 12V power which supplies a large amount of current...

Страница 34: ...ence board and all its I O cards VCC_12 VCC_12V_BULK VCC_5V_STBY and VCC_RTC_BAT are provided from the reference board In addition the P5040 P5020RDB PS provides all the voltages necessary for correct...

Страница 35: ...olt age up to 30A 1 tolerance The same chip is also used to supply VDD_PL platform voltage 5 3 1 2 PDN Options Figure 18 shows various main power supplies combination used for different DUT types depe...

Страница 36: ...chitecture Figure 18 P5040 P5020RDB PDN Options 5 3 1 3 DDR DDR SDRAM GVDD termination M_VTT and reference M_VREF voltages are automatically set at the noted limits depending on SW1 6 DRAM TYPE follow...

Страница 37: ...ese characteristics Powers the SERDES block IO Voltage value is set to 1 5 or 1 8V using SW3 5 or a corresponding FPGA control bit 5 3 1 7 VDD_CORE VDD_CB voltage has the following characteristics Pow...

Страница 38: ...or U21 When the main ATX PS is powered and connected to the RDB VCC_HOT3V3 is present then voltage is supplied to the CPU Alternatively the battery can supply voltage if J9 is shorted Auxiliary J10 VD...

Страница 39: ...nections for the P5040 P5020 Conversely the reference board provides a battery to the RTC clock to keep time while the system is turned off This table summarizes P5040 P5020 clock distribution NOTE DD...

Страница 40: ...tribution Clock Frequency Destination Device SYSCLK 33 200 MHz SYSCLK IDT ICS307M 02 tR typ 1ns tF typ 1ns Duty cycle 60 Jitter type 120 ps 25MHz input clock oscillator RTC 50KHz RTCCLK FPGA SD_REF_CL...

Страница 41: ...either RRST or XRST PX_AUX is the exception it is ONLY reset by RRST and is unaffected by COP_HRST and wdog_rst If the watchdog timer expires then all internal settings are reset This includes VELA c...

Страница 42: ...to clear 2 Configures and releases the processor from reset 3 Idles waiting for further reset conditions to occur This table summarizes the reset conditions and actions of the FPGA Table 21 Reset Con...

Страница 43: ...Asserted low until ATX power supply is stable while system reset is asserted e g motherboard switch or chassis cable switch Asserted only after the following Power ON is asserted Intervention by a ma...

Страница 44: ...DIP switches Figure 20 Configuration Logic Configuration logic has several options as follows ngPIXIS by default transfers switch settings to the processor configuration pin during the HRESET_B assert...

Страница 45: ...ch the name on the schematics and on the printed circuit board in most cases except where a spare has been newly assigned and only the FPGA has changed 6 2 1 Configuration Switches For those signals c...

Страница 46: ...and switch configurations This table provides a summary of switch configurations Table 24 Configuration Switch Format Switch Bit DIP Switch Label 1 2 3 4 5 6 7 8 ngPIXIS Register Bit Power Architectur...

Страница 47: ...cription 1 2 SW_CFG_GPINPUT 0 1 Static 3 4 SW_CFG_SVR 0 1 5 SW_TESTSEL_B 6 7 SW_PROC_SEL 0 1 8 SW_I2C1_PROC_ISO SW8 see Switch 8 SW8 description 1 SW_FORCE_I2C_OPEN Static 2 SW_I2C_RCW_WP 3 SW_FLASH_W...

Страница 48: ...GWP 5 ATX PS System Power ON OFF after ATX_PS ON SW_RP_CNTRL 6 spare6 7 8 cfg_cfgopt 0 1 System Config Switches I2C Content 0 1 Static SW15 see Switch 15 SW15 description 1 4 PDN_CFG 0 3 Static 5 SW_P...

Страница 49: ...TAG Data R FPGA build data dependant 0x10 PX_VCTL VELA Control R W 0x00 0x11 PX_VSTAT VELA Status R 0x00 0x12 PX_HSTAT P5040 P5020RDBP5040 P5020 Status R 0x03 0x13 Reserved Reserved Reserved Undefined...

Страница 50: ...t board revision a software visible and impacting change for example replacing a component with a slot or eliminating a backup device NOTE Changing a FLASH manufacturer is not considered an architectu...

Страница 51: ...GA features are added corrected Increments as FPGA images are distributed FPGA images are generally designed to work on one or more board versions therefore there is no correlation between them Figure...

Страница 52: ...5 6 7 R EVESRC 9999 LED FAIL W Reset 0 X X X 0 0 0 0 Offset 0x03 Table 30 PX_CSR Field Descriptions Bits Name Description 0 2 33EVESRC Selects one of several inputs for mapping to an internal signal e...

Страница 53: ...miscellaneous board features see schematics and or documentation 0 GEN_RST_B is asserted 1 GEN_RST_B is deasserted 1PX_RST register bits cannot reset independently 2 PX_RST ALL only resets during a fu...

Страница 54: ...y Register PX_AUX 3 SDREFCLK3_QD_EN Enables disables Serdes Reference Clock to Bank 3 0 disabled 1 enabled 4 USBCLK_EN Enables disables USB Clock Oscillator 0 disabled 1 enabled 5 SDREFCLK4_QE_EN Enab...

Страница 55: ...0 0 X X X Offset 0x07 Table 34 PX_SPD Field Descriptions Bits Name Description 0 1 PIXISOPT Reflects SW12 1 2 settings 2 4 Reserved 0 5 7 SYSCLK Reflects SW5 6 8 settings see Table 35 Table 35 SYSCLK...

Страница 56: ...d I2 C41 1 Integrated I2 C4 I2 C2 1Bit 1 used for P5040 P5020 2 NGI2 C_ACC Controls CPU access to I2 C1 connected devices owned by ngPIXIS FPGA EEPROM FPGA Configuration Data and EEPROM FPGA ExConfigu...

Страница 57: ...4 5 6 7 R EMI1_SEL1 EMI1_SEL0 EMI1_SEL_E N SPI_I2 C_SEL W Reset 0 0 0 0 1 0 0 1 Offset 0x09 Table 38 PX_BRDCFG1 Field Descriptions1 1 See reg_BRDCFG2 1 2 for extra control signals Bits Name Descripti...

Страница 58: ...IS GMSA core 7 1 12 Board Configuration Register PX_BRDCFG2 This register controls board configurations they can be changed at any time Figure 33 Board Configuration Register 2 PX_BRDCFG2 Table 39 MII...

Страница 59: ...drives MII Management EMI1_SEL 0 1 FPGA PX_BRDCFG1 1 3 6 drives MII Management EMI2_SEL0 Not Applicable 0 GPIO2 1 FPGA 2 GPIO0 drives EMI1_SEL0 GPIO1 drives EMI1_SEL1 GPIO2 drives EMI1_SEL1 GPIO3 dri...

Страница 60: ...P or watchdog initiated resets Figure 35 Power Status Register PX_DATA 0 1 2 3 4 5 6 7 R R W GPIO 0 R W GPIO1 R W GPIO 2 R W GPIO 3 R W GPIO 4 R W GPIO 5 R W GPIO 6 R W GPIO 7 W Reset 0 0 0 0 0 0 0 0...

Страница 61: ...formation embedded FPGA build date minor revisions image name and so on NOTE Type ngPIXIS INFO under eDINK to display FPGA TAG register data Figure 37 TAG Register PX_TAG 7 1 17 VELA Control Register...

Страница 62: ...ation sequencer activity NOTE Not supported for P5040 P5020RDB 0 1 2 3 4 5 6 7 R WDEN PWROFF GO W Reset 0 0 0 0 0 0 0 0 Offset 0x10 Table 45 PX_VCTL Field Descriptions Bits Name Description 0 3 Reserv...

Страница 63: ...The OCM control status register is a general purpose R W register that communicates between P5040 P5020 and the FPGA GMSA processor 0 1 2 3 4 5 6 7 R BUSY W Reset 0 0 0 0 0 0 0 0 Offset 0x11 Table 46...

Страница 64: ...icate between P5040 P5020 and the FPGA GMSA processor NOTE Not applicable for P5040 P5020RDB Figure 42 Configuration Sequencer Status Register PX_OCMMSG 0 1 2 3 4 5 6 7 R ACK U0 DBGSEL U1 MSG W Reset...

Страница 65: ...trolled sequencer The selected watchdog works independently of other watchdog timers for example those within P5040 P5020 Figure 44 Watchdog Register PX_WATCH Table 49 PX_OCMMSG Field Descriptions Bit...

Страница 66: ...01326592sec 2 01326592sec This table lists examples of PX_WATCH register values 7 1 24 Switch Register PX_SWx The switch register defines configuration switch overrides Each SWx register and its bits...

Страница 67: ...x 3 SWx 4 SWx 5 SWx 6 SWx 7 SWx 8 W Reset 0 0 0 0 0 0 0 0 Offset 0x20 0x22 0x24 Table 53 PX_SW 1 8 Field Descriptions Bits Name Description 0 7 SWx b Values that will replace switch SWx b 0 1 2 3 4 5...

Страница 68: ...em data such as the board ID errata as shipped manufacturing date and Ethernet MAC address 0 1 2 3 4 5 6 7 R GPIO_OUT 0 GPIO_OUT 1 GPIO_OUT 2 GPIO_OUT 3 GPIO_OUT 4 GPIO_OUT 5 GPIO_OUT 6 GPIO_OUT 7 W R...

Страница 69: ...vice Data content is described in detail in AN3638 The SystemID Format for Power Architecture Development Systems the document is found on the http www freescale com website 8 Revision History This ta...

Страница 70: ...40 P5020 Appendix A Reference board Switch Assignments and Defaults When Used with P5040 P5020 NOTE For the default settings listed in the tables below ON 1 and OFF 0 The following tables describe the...

Страница 71: ...Board User Guide Rev 0 Freescale Semiconductor 71 Reference board Switch Assignments and Defaults When Used with P5040 P5020 Figure 50 Switch 2 SW2 description This figure describes switch 3 SW3 Figur...

Страница 72: ...ev 0 72 Freescale Semiconductor Reference board Switch Assignments and Defaults When Used with P5040 P5020 This figure describes switch 5 SW5 Figure 52 Switch 5 SW5 description This figure describes s...

Страница 73: ...Reference Design Board User Guide Rev 0 Freescale Semiconductor 73 Reference board Switch Assignments and Defaults When Used with P5040 P5020 This figure describes switch 7 SW7 Figure 54 Switch 7 SW7...

Страница 74: ...ev 0 74 Freescale Semiconductor Reference board Switch Assignments and Defaults When Used with P5040 P5020 This figure describes switch 8 SW8 Figure 55 Switch 8 SW8 description This figure describes s...

Страница 75: ...Freescale Semiconductor 75 Reference board Switch Assignments and Defaults When Used with P5040 P5020 This figure describes switch 11 SW11 Figure 57 Switch 11 SW11 description This figure describes s...

Страница 76: ...Rev 0 76 Freescale Semiconductor Reference board Switch Assignments and Defaults When Used with P5040 P5020 This figure describes switch 15 SW15 Figure 59 Switch 15 SW15 description This table descri...

Страница 77: ...may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be...

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