NXP Semiconductors P4080, Руководство пользователя, Страница: 26 / 60

P4080 Development System User’s Guide, Rev. 0
26 Freescale Semiconductor
Architecture
5.1.15 EM1 and EM2 Management Busses
The P4080 has two types buses: one for SGMII and RGMII PHY management, and one for XAUI PHY
management. Because one set of busses must span across multiple devices in the P4080DS system,
multiplexers are used to route from the P4080 to each PHY. GPIOs are used to control the multiplexers.
These tables summarize the management bus control.
2 0x4C Processor Thermal Monitor
Analog ADT7461A or equivalent —
2 0x51 DDR3 DIMM Socket 1
Atmel AT24C02, Microchip
MCP98242. or equivalent SPD EEPROM
Type of device depends on the DIMM vendor; the default Elpida
device supplies an MCP98242.
2 0x52 DDR3 DIMM Socket 2
Atmel AT24C02, Microchip
MCP98242. or equivalent SPD EEPROM
Type of device depends on the DIMM vendor; the default Elpida
device supplies an MCP98242.
2 0x68 Real-time clock
DS3232 Optional
2 n/a ngPIXIS I2C port Used for bus reset, monitoring, and master-only data collection.
2 n/a I2C Access Header For remote programming of boot sequencer startup code (if
needed).
3 0x6E SerDes clock generator
ICS9FG108 —
3 n/a I2C Access Header For remote programming (if needed).
Note: These addresses do not include the position of the LSB of the transmitted address (the read/write bit).
Table 11. PHY Management Bus Map for EMI1
Bus GPIO[0:1] Device
EMI1 00 On board Vitesse RGMII
EMI1 01 Slot 4 SGMII
EMI1 10 Slot 3 SGMII
EMI1 11 Slot 5 SGMII
Table 12. PHY Management Bus Map for EMI2
Bus GPIO[2:3] Device
EMI2 00 No Device
EMI2 01 Slot 4 XAUI
Table 10. I2C Bus Device Map (continued)
I
2
C Bus
I
2
C
Address
Device Notes