NXP Semiconductors MPC5644A, Справочное руководство, Страница: 1609 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1609
The CHI LRAM is accessed by the application via regular register read and write accesses.
33.6.24 Memory content error detection
The FlexRay module provides integrated memory content error detection for both the CHI LRAM and PE
DRAM, and memory content error correction for the PE DRAM. The memory error detection for the CHI
LRAM uses an standard Hamming code with a Hamming distance of 3 and detects all single-bit and
double-bit errors (SEDDED). The memory error detection and correction for the PE DRAM uses an
enhanced Hamming code with a Hamming distance of 4 and detects and corrects all single-bit errors and
detects all double-bit errors (SECDED).
This section describes the reporting of the occurrence of memory content errors, the reaction of the module
on the occurrence, and how the application can inject memory errors in order to trigger the report and
response behavior.
33.6.24.1 Memory error types
A memory error is the distortion of one or more bits read out of the memory. The reading of the values of
all zeros and all ones is considered as an special case. The FlexRay module detects and indicates the
memory errors as shown in
Table 33-130 . The entries on the top have higher priority.
Each memory read access reads out all banks of the addressed row, and runs error detection on all banks,
even in the case that the application has triggered a read from only one bank. This may lead to the reporting
of an memory error if at least one bank contains a memory error, even if an error free bank has been read.
Table 33-129. CHI LRAM layout
AD
R
BANK5 BANK4 BANK3 BANK2 BANK1 BANK0
0x0
0
FR_MBIDXR1 FR_MBFIDR1 FR_MBCCFR1 FR_MBIDXR0 FR_MBFIDR0 FR_MBCCFR0
0x0
1
FR_MBIDXR3 FR_MBFIDR3 FR_MBCCFR3 FR_MBIDXR2 FR_MBFIDR2 FR_MBCCFR2
...
0x1
F
FR_MBIDXR12
7
FR_MBFIDR12
7
FR_MBCCFR12
7
FR_MBIDXR12
6
FR_MBFIDR12
6
FR_MBCCFR12
6