NXP Semiconductors MPC5605BK, Справочное руководство

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Chapter 24 LIN Controller (LINFlexD)
MPC5606BK Microcontroller Reference Manual, Rev. 2
486 Freescale Semiconductor
24.9.4 UART receiver
Reception of a data byte is started as soon as the software completes the following tasks in order:
1. Exits Initialization mode
2. Sets the UARTCR[RXEN] field
3. Detects the start bit
There is a dedicated data buffer for received data bytes. Its size is as follows:
• 4 bytes when UARTCR[WL1] = 0
• 2 half-words when UARTCR[WL1] = 1
After the programmed number (RDFL bits) of bytes has been received, the UARTSR[DRFRFE] field is
set. If the UARTCR[RXEN] field is cleared during a reception, the current reception is completed, but no
further reception can be invoked until UARTCR[RXEN] is set again.
The buffer can be configured in FIFO mode (required when DMA Rx is enabled) by setting
UARTCR[RFBM].
Table 24-6. BDRL access in UART mode
Access Mode
1
1
As specified by UARTCR[TFBM]
Word length
2
2
As specified by the WL1 and WL0 bits of the UARTCR register. In UART FIFO mode (UARTCR[TFBM] = 1),any
read operation causes an IPS transfer error.
IPS operation result
Write Byte0 FIFO Byte OK
Write Byte1-2-3 FIFO Byte IPS transfer error
Write Half-word0-1 FIFO Byte IPS transfer error
Write Word FIFO Byte IPS transfer error
Write Byte0-1-2-3 FIFO Half-word IPS transfer error
Write Half-word0 FIFO Half-word OK
Write Half-word1 FIFO Half-word IPS transfer error
Write Word FIFO Half-word IPS transfer error
Read Byte0-1-2-3 FIFO Byte/Half-word IPS transfer error
Read Half-word0-1 FIFO Byte/Half-word IPS transfer error
Read Word FIFO Byte/Half-word IPS transfer error
Write Byte0-1-2-3 BUFFER Byte/Half-word OK
Write Half-word0-1 BUFFER Byte/Half-word OK
Write Word BUFFER Byte/Half-word OK
Read Byte0-1-2-3 BUFFER Byte/Half-word OK
Read Half-word0-1 BUFFER Byte/Half-word OK
Read Word BUFFER Byte/Half-word OK