NXP Semiconductors MPC5602S, Справочное руководство

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Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 139
Several Channel Interrupt Pending Registers are also provided in order to signal which of the channels’
measurement has been completed.
The analog watchdog interrupts are handled by two 8-bit registers, WTISR (Watchdog Threshold Interrupt
Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register), in order to check and enable
the interrupt request to the EIC module. The Watchdog interrupt source sets two pending bits—WDG
x H
and WDG x L—in the WTISR for each of the four channels being monitored.
The CEOCFR contains the interrupt pending request status. If the user wants to clear a particular interrupt
event status, then writing a 1 to the corresponding status bit clears the pending interrupt flag (at this write
operation all the other bits of the CEOCFR must be maintained at 0).
5.3.7 External decode signals delay
The ADC provides several external decode signals to select which external channel has to be converted.
In order to take into account the control switching time of the external analog multiplexer, a Decode
Signals Delay register (DSDR) is provided. The delay between the decoding signal selection and the actual
start of conversion can be programmed by writing the field DSD[0:7]. When this programmed delay is
taking place, the ADCSTATUS[0:2] field in the Main Status Register (MSR) will display the value 010
(wait state).
5.3.8 Power-down mode
The analog part of the ADC can be put in low-power mode by setting the PWDN bit in the MCR. After
releasing the reset signal the ADC analog module is kept in power-down mode by default, so this state
must be exited before starting any operation by resetting the appropriate bit in the MCR.
The power-down mode can be requested at any time by setting the PWDN bit in the MCR. If a conversion
is ongoing, the ADC hard macrocell cannot immediately enter the power-down mode. In fact, the ADC
enters power-down mode only after completing the ongoing conversion. Otherwise, the ongoing operation
should be aborted manually by resetting the NSTART bit and using the ABORTCHAIN bit.
Bit ADCSTATUS[0] in the MSR is set only when ADC enters power-down mode.
After the power-down phase is completed the process ongoing before the power-down phase must be
restarted manually (by setting the appropriate START bit).
Resetting PWDN bit and setting NSTART or JSTART bit during the same cycle is forbidde
5.3.9 Auto-clock-off mode
To reduce power consumption during the Idle mode of operation (without going into power-down mode),
an “auto-clock-off” feature can be enabled by setting the ACKO bit in the MCR. When enabled, the analog
clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed
by the user.