NXP Semiconductors MKW01Z128, Справочное руководство

Страница: 477 / 884

MCG_S field descriptions (continued)
Field Description
0 PLL has not lost lock since LOLS 0 was last cleared.
1 PLL has lost lock since LOLS 0 was last cleared.
6
LOCK0
Lock Status
This bit indicates whether the PLL has acquired lock. Lock detection is only enabled when the PLL is
enabled (either through clock mode selection or PLLCLKEN0=1 setting). While the PLL clock is locking to
the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets
asserted. If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in the C5 register or the
VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has
reacquired lock. Loss of PLL reference clock will also cause the LOCK0 bit to clear until the PLL has
reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes the lock status bit to
clear and stay cleared until the Stop mode is exited and the PLL has reacquired lock. Any time the PLL is
enabled and the LOCK0 bit is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
again.
0 PLL is currently unlocked.
1 PLL is currently locked.
5
PLLST
PLL Select Status
This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a
write to the PLLS bit due to internal synchronization between clock domains.
0 Source of PLLS clock is FLL clock.
1 Source of PLLS clock is PLL output clock.
4
IREFST
Internal Reference Status
This bit indicates the current source for the FLL reference clock. The IREFST bit does not update
immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0 Source of FLL reference clock is the external reference clock.
1 Source of FLL reference clock is the internal reference clock.
3–2
CLKST
Clock Mode Status
These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the
CLKS bits due to internal synchronization between clock domains.
00 Encoding 0 — Output of the FLL is selected (reset default).
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Output of the PLL is selected.
1
OSCINIT0
OSC Initialization
This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have
completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC
module's detailed description for more information.
0
IRCST
Internal Reference Clock Status
The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The
IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization
between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled,
either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit .
Table continues on the next page...
Memory Map/Register Definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
346 Freescale Semiconductor, Inc.